IP Library Granted Patent US 8,121,713
Granted Patent B2
US 8,121,713 · App. 11/663,008 · Granted Feb 21, 2012

Electronic apparatus, method for generating digital signal, digital signal recording medium, and signal processing apparatus

Assignee: Yamaha Corporation
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Quick Facts
Patent No.
US 8,121,713
App. No.
11/663,008
Granted
Feb 21, 2012
Kind
B2
Abstract

An electronic apparatus having a CPU for controlling each portion of the apparatus has a storage unit for storing at least one of firmware or data to be used by the CPU, an input terminal to which a digital signal with a predetermined format is input, a processing unit for performing a predetermined process on the digital signal input from the input terminal, an extracting unit for extracting data located at predetermined timings in one frame of the digital signal input from the input terminal, and outputting the data as extracted data, and a rewriting unit for analyzing the extracted data and rewriting at least one of the firmware or the data in the storage unit based on a result of the analysis and the extracted data. The CPU at least serves as the extracting unit.

Claims (20)

1. An electronic apparatus having a CPU for controlling each portion of the apparatus, the apparatus comprising:

a storage unit that stores firmware for operating the CPU;

an input terminal complying with a digital audio interface standard for receiving a digital audio signal;

a processing unit that performs a predetermined process on the digital audio signal received by the input terminal;

an extracting unit that extracts data located at predetermined timings in one frame of the digital audio signal received by the input terminal, and outputs the extracted data as extracted firmware data; and

a rewriting unit that analyzes the extracted form data and rewrites the firmware in the storage unit based on a result of the analysis and the extracted firmware data,

wherein the CPU serves at least as the extracting unit,

wherein the one frame has an effective data length of N segments, and

wherein the predetermined timings are located in sampling points set in at least one of the N segments.

2. The electronic apparatus according to claim 1 , wherein the CPU further serves as the rewriting unit.

3. The electronic apparatus according to claim 1 , wherein the CPU supplies the extracted firmware data to the processing unit, and the processing unit serves as the rewriting unit.

4. The electronic apparatus according claim 1 , further comprising:

a buffer storage unit that stores the extracted firmware data temporarily,

wherein the rewriting unit analyzes the extracted data stored in the buffer storage unit sequentially, and rewrites the firmware in the storage unit based on a result of the analysis and the extracted firmware data in the buffer storage unit.

5. The electronic apparatus according to claim 1 , wherein the predetermined timings are located in sampling points set in each of the N segments.

6. The electronic apparatus according to claim 1 , wherein the predetermined timings are located in sampling points set in M segments among the N segments, where M is smaller than N.

7. The electronic apparatus according to claim 1 , wherein the rewriting unit performs the analysis and the rewriting the firmware while ignoring, of the extracted data extracted by the extracting unit, data located in specific timings.

8. The electronic apparatus according to claim 5 , wherein:

each of the segments has a same number of bits, and

bits belong to each segment have the same value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2007
From: MURAMATSU, AKIHIRO; SUYAMA, AKIHIKO
To: YAMAHA CORPORATION
Reel/Frame 019058/0408 →
Priority Claims (2)
JP 2004-268248 · Sep 15, 2004 · national
JP 2004-268249 · Sep 15, 2004 · national
Continuity (1)
Related Publication 20080005540A1 · Jan 3, 2008