Method for fabricating semiconductor device

1. A method for fabricating a semiconductor device, comprising:

forming a plurality of first trenches by etching a substrate;

forming a plurality of buried bit lines in the first trenches;

forming a plurality of second trenches to expose at least one sidewall of the buried bit lines by etching the substrate; and

forming a plurality of one-sidewall contact plugs which fill the second trenches,

wherein the buried bit lines and the one-sidewall contact plugs are line-type patterns, which extend in a first direction.

2. The method of claim 1 , wherein the forming of the plurality of one-sidewall contact plugs comprises:

forming the plurality of second trenches, which extend in the first direction and are parallel to each other, by etching the substrate;

forming a conductive layer for the one-sidewall contact plugs over the entire resultant structure having the second trenches formed therein;

forming the one-sidewall contact plugs by performing an etch back process such that the conductive layer remains with a certain thickness within the second trenches; and

forming an insulation layer over the one-sidewall contact plugs within the second trenches.

3. The method of claim 2 , wherein the etch back process is performed in such a manner that the conductive layer remains with a volume ranging from approximately 20% to approximately 60% of a volume of the second trenches.

4. The method of claim 2 , wherein the insulation layer is formed by an oxidation process.

5. The method of claim 1 , wherein a width of the second trenches ranges from approximately 5% to approximately 15% of a depth of the first trenches, and a depth of the second trenches ranges from approximately 70% to approximately 90% of the depth of the first trenches.

6. The method of claim 1 , wherein the buried bit lines comprise a metallic silicide layer.

7. The method of claim 1 , wherein the one-sidewall contact plugs comprise a doped polysilicon layer or a metallic layer.

8. The method of claim 1 , further comprising:

forming an inter-layer dielectric layer over the entire resultant structure having the one-sidewall contacts formed therein;

forming a plurality of third trenches by selectively etching the inter-layer dielectric layer to expose a surface of the substrate in a region distinct from regions where the buried bit lines and the one-sidewall contact plugs are formed; and

forming a plurality of pillars in the third trenches by using an epitaxial growth process.

9. The method of claim 8 , wherein the inter-layer dielectric layer is formed with a thickness ranging from approximately 1,000 Å to approximately 2,000 Å.

10. The method of claim 8 , wherein the forming of the plurality of third trenches comprises:

forming a mask pattern over the resultant structure having the interlayer dielectric layer formed therein, the mask pattern having a plurality of openings arranged in the first direction and a second direction crossing over the first direction while covering the regions where the buried bit lines and the one-sidewall contacts are formed; and

forming the third trenches by etching the inter-layer dielectric layer using the mask pattern as an etching barrier.

11. The method of claim 8 , further comprising:

removing the inter-layer dielectric layer to expose the pillars;

forming a gate dielectric layer over the entire surfaces of the pillars; and

forming a plurality of word lines, which extend in the second direction and are parallel to each other.

12. The method of claim 1 , further comprising:

forming an inter-layer dielectric layer over the entire resultant structure having the one-sidewall contact plugs formed therein;

forming a plurality of first mask patterns over the inter-layer dielectric layer, the first mask patterns extending in the first direction and being parallel to each other, while covering regions where the buried bit lines and the one-sidewall contact plugs are formed;

forming a plurality of line-type trenches, exposing a surface of the substrate, by etching the inter-layer dielectric layer using the first mask patterns as an etching barrier;

forming a plurality of active regions in the line-type trenches by using an epitaxial growth process;

forming a plurality of second mask patterns over the resultant structure having the active regions formed therein, the second mask patterns extend in a second direction and are parallel to each other, and cross over the first direction while covering pillar formation regions; and

forming a plurality of pillars arranged in the first and second directions by etching the active regions and the inter-layer dielectric layer using the second mask patterns as an etching barrier.

13. The method of claim 12 , wherein, in the forming of the plurality of pillars, an etching process is performed in such a condition that an etching selectivity of the active regions with respect to the inter-layer dielectric layer is low.

14. A method for fabricating a semiconductor device, comprising:

forming a plurality of first line-type trenches by etching a substrate;

forming a plurality of bit lines buried in the first trenches;

forming a plurality of second line-type trenches to expose one sidewall of the bit lines by etching the substrate;

forming a plurality of one-sidewall contact plugs which fill the second trenches;

forming an inter-layer dielectric layer over the entire resultant structure having the one-sidewall contact plugs formed therein;

forming a plurality of third trenches by selectively etching the inter-layer dielectric layer to expose a surface of the substrate in a region distinct from regions where the buried bit lines and the one-sidewall contact plugs are formed; and

forming a plurality of pillars buried in the third trenches.

15. The method of claim 14 , wherein the forming of the plurality of pillars is performed by an epitaxial growth process.