Method and apparatus for a radiation detector
View Patent ↗The invention is directed at a radiation detector which includes a grid electrode located within the detector to assist in the charge collection process. The grid electrode is preferably embedded within a semiconductor layer between two electrode layers, one of the electrode layers being a charge collecting electrode and the other being a common electrode.
1. A radiation detector comprising:
a first electrode layer;
at least one grid electrode;
a second electrode layer;
at least one semiconductor layer, deposited, via a deposition process, between the first and second electrode layers; and
wherein the at least one grid electrode is embedded in one of the at least one semiconductor layers.
2. The radiation detector of claim 1 wherein there are two semiconductor layers and one grid electrode and the grid electrode is located between the first and second semiconductor layers.
3. The radiation detector of claim 1 further comprising a substrate layer located beneath the first electrode layer.
4. The radiation detector of claim 3 wherein the substrate further comprises readout electronics.
5. The radiation detector of claim 4 wherein the substrate is a thin film transistor (TFT) array or a CMOS electronic pixel array.
6. The radiation detector of claim 5 wherein the TFT array is made of amorphous silicon, polycrystalline silicon or Cadmium Selenide.
7. The radiation detector of claim 5 wherein the CMOS electronic pixel array is a crystalline silicon CMOS electronic pixel array.
8. The radiation detector of claim 5 wherein the array is not aligned with the grid electrode.
9. The detector of claim 1 wherein the deposition process is one of physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition.
10. A method of creating a radiation detector comprising:
depositing a first electrode layer, on top of a substrate;
depositing a semiconductor layer or insulator layer on top of the first electrode layer;
embedding a grid electrode within the semiconductor layer;
depositing a second electrode layer, on top of the semiconductor layer.
11. The method of claim 10 wherein depositing a first electrode layer comprises depositing a layer of transparent conductive oxide, metal or doped semi-conductor, or Indium Tin Oxide (ITO).
12. The method of claim 10 wherein embedding comprises:
depositing a conductive layer on the semiconductor layer or insulator layer; and
patterning the conductive layer.
13. The method of claim 12 further including:
patterning the semiconductor layer or the insulator layer.
14. The method of claim 13 wherein patterning comprises:
using photolithography or a shadow mask.
15. The method of claim 13 wherein patterning comprises:
depositing a photoresist layer over at least one of the semiconductor layer or conductive layer;
placing a mask over the photoresist layer;
transmitting ultraviolet light towards the mask; and
etching weak areas of photoresist layer created by the transmission of light.