Virtual barrier synchronization cache
View Patent ↗A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
1. A data processing system, comprising:
an interconnect fabric;
a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs);
a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory, wherein each of the plurality of processing units includes:
a processor core; and
a cache memory coupled to the processor core, said cache memory including:
a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory; and
a cache controller that, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
2. The data processing system of claim 1 , wherein the VBSR update command comprises a single address tenure specifying both an address of the particular VBSR line and an updated data value of the VBSR line.
3. The data processing system of claim 1 , wherein:
the cache memory comprises a VBSR cache memory dedicated to caching data from the virtual barrier synchronization region of system memory; and
each of the plurality of processing units further includes a separate multi-level cache hierarchy for caching data outside the virtual barrier synchronization region of system memory.
4. The data processing system of claim 3 , wherein said processing unit further includes a non-cacheable unit that services non-cacheable memory access requests of the processor core, wherein the non-cacheable unit includes the VBSR cache memory.
5. The data processing system of claim 1 , wherein:
the cache controller, responsive to determining that the store request results in a miss, issues a VBSR get command on the interconnect fabric to obtain a copy of the particular VBSR line to update; and
the cache array has an associated buffer that buffers the copy of the particular VBSR line and associated merge logic that merges any VBSR update commands in process with the copy of the particular VBSR line prior to the copy of the particular VBSR line being cached in the cache array.
6. The data processing system of claim 1 , wherein:
the cache controller includes a directory of contents of the cache array;
the cache controller, responsive to selection of the particular VBSR line for eviction, determines if the directory indicates that the cache controller has responsibility to writeback the particular VBSR line to the system memory, and if so, passes the responsibility to another cache controller via an election process.
7. A processing unit for a multiprocessor data processing system including an interconnect fabric, a system memory including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region, wherein the processing unit comprises:
a processor core; and
a cache memory coupled to the processor core, said cache memory including:
a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory; and
a cache controller that, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
8. The processing unit of claim 7 , wherein the VBSR update command comprises a single address tenure specifying both an address of the particular VBSR line and an updated data value of the VBSR line.
9. The processing unit of claim 7 , wherein:
the cache memory comprises a VBSR cache memory dedicated to caching data from the virtual barrier synchronization region of system memory; and
the processing unit further includes a separate multi-level cache hierarchy for caching data outside the virtual barrier synchronization region of system memory.
10. The processing unit of claim 9 , wherein said processing unit further includes a non-cacheable unit that services non-cacheable memory access requests of the processor core, wherein the non-cacheable unit includes the VBSR cache memory.
11. The processing unit of claim 7 , wherein:
the cache controller, responsive to determining that the store request results in a miss, issues a VBSR get command on the interconnect fabric to obtain a copy of the particular VBSR line to update; and
the cache array has an associated buffer that buffers the copy of the particular VBSR line and associated merge logic that merges VBSR update commands in process with the copy of the particular VBSR line prior to the copy of the particular VBSR line being cached in the cache array.
12. The processing unit of claim 7 , wherein:
the cache controller includes a directory of contents of the cache array;
the cache controller, responsive to selection of the particular VBSR line for eviction, determines if the directory indicates that the cache controller has responsibility to writeback the particular VBSR line to the system memory, and if so, passes the responsibility to a cache controller of another processing unit via an election process.
13. The processing unit of claim 7 , wherein the processing unit is a single integrated circuit.
14. A method of data processing in a data processing system including an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region, said method comprising:
a cache of a first processing unit among the plurality of processing units holding a plurality of VBSRs including a particular VBSR line from the virtual barrier synchronization region of the system memory;
a processor core of the first processing unit issuing a store request to update the particular VBSR line; and
a cache controller of the cache, responsive to the store request from the processor core to update a particular VBSR line, performing a non-blocking update of a cache array in each other of the plurality of processing units holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
15. The method of claim 14 , wherein the VBSR update command comprises a single address tenure specifying both an address of the particular VBSR line and an updated data value of the VBSR line.
16. The method of claim 14 , wherein:
the cache memory comprises a VBSR cache memory dedicated to caching data from the virtual barrier synchronization region of system memory; and
said method further comprises the first processing unit caching data outside the virtual barrier synchronization region of system memory in a multi-level cache hierarchy separate from the VBSR cache memory.
17. The method of claim 16 , wherein:
said processing unit further includes a non-cacheable unit including the VBSR cache memory; and
the issuing comprises the processor core issuing the store request as a non-cacheable store request.
18. The method of claim 14 , and further comprising
the cache controller, responsive to determining that the store request results in a miss, issues a VBSR get command on the interconnect fabric to obtain a copy of the particular VBSR line to update; and
buffering the copy of the particular VBSR line received from the interconnect fabric; and
while buffering the copy of the particular VBSR line, merging any VBSR update commands in process with the copy of the particular VBSR line prior to the copy of the particular VBSR line being cached in the cache array.
19. The method of claim 14 , wherein:
the cache controller includes a directory of contents of the cache array;
the method further comprises the cache controller, responsive to selection of the particular VBSR line for eviction, determining if the directory indicates that the cache controller has responsibility to writeback the particular VBSR line to the system memory, and if so, passing the responsibility to another cache controller via an election process.