Inter-phase skew detection circuit for multi-phase clock, inter-phase skew adjustment circuit, and semiconductor integrated circuit

1. An inter-phase skew detection circuit comprising:

a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks, where N is an integer of 2 or greater;

a phase comparison target clock generation circuit that generates N phase comparison target clocks by using predetermined N frequency-divided clocks among the N+2 frequency-divided clocks;

a phase comparison reference clock generation circuit that generates N reference clocks by using the N+2 frequency-divided clocks, in accordance with predetermined combinations between the N+2 frequency-divided clocks and an operation criterion; and

a phase comparison circuit that detects respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks.

2. The inter-phase skew detection circuit in accordance with claim 1 , wherein:

the frequency division circuit receives the N-phase clocks which are 4-phase clocks consisting of first, second, third, and fourth phase clocks, and sequentially generates six frequency-divided clocks consisting of first, second, third, fourth, fifth, and sixth frequency-divided clocks respectively in synchronism with the fourth phase clock, the first phase clock, the second phase clock, the third phase clock, the fourth phase clock, and the first phase clock, where each frequency-divided clock has a period twice as much as that of each 4-phase clock;

the phase comparison target clock generation circuit delays each of four frequency-divided clocks including the second frequency-divided clock to the fifth frequency-divided clock among the six frequency-divided clocks by a predetermined delay amount, so as to generate four phase comparison target clocks consisting of first, second, third, and fourth phase comparison target clocks;

the phase comparison reference clock generation circuit generates four reference clocks consisting of first, second, third, and fourth reference clocks based on the six frequency-divided clocks, wherein for four combinations of the first frequency-divided clock and the third frequency-divided clock, the second frequency-divided clock and the fourth frequency-divided clock, the third frequency-divided clock and the fifth frequency-divided clock, and the fourth frequency-divided clock and the sixth frequency-divided clock, each of the reference clocks is generated by adding together both frequency-divided clocks in each combination and dividing the sum thereof by 2; and

the phase comparison circuit detects four respective phase differences between the four phase comparison target clocks and the corresponding four reference clocks.

3. The inter-phase skew detection circuit in accordance with claim 2 , wherein:

the phase comparison reference clock generation circuit uses a phase interpolators for generating each of the reference clocks by adding together both frequency-divided clocks in each combination and dividing the sum thereof by 2; and

the phase comparison target clock generation circuit delays said each of four frequency-divided clocks by an amount of delay corresponding to a delay time of an output signal generated in the phase interpolator.

4. The inter-phase skew detection circuit in accordance with claim 1 , wherein:

the frequency division circuit receives the N-phase clocks consisting of first, second, third, . . . , and Nth phase clocks, and sequentially generates N+2 frequency-divided clocks consisting of first, second, third, . . . , (N+2)th frequency-divided clocks respectively in synchronism with the Nth phase clock, the first phase clock, the second phase clock, . . . , the (N−1)th phase clock, the Nth phase clock, and the first phase clock, where each frequency-divided clock has a period twice as much as that of each N-phase clock;

the phase comparison target clock generation circuit delays each of N frequency-divided clocks including the second frequency-divided clock to the (N+1)th frequency-divided clock among the N+2 frequency-divided clocks by a predetermined delay amount, so as to generate N phase comparison target clocks consisting of first, second, third, . . . , and Nth phase comparison target clocks;

the phase comparison reference clock generation circuit generates N reference clocks consisting of first, second, third, . . . , and Nth reference clocks based on the N+2 frequency-divided clocks, wherein for N combinations of the first frequency-divided clock and the third frequency-divided clock, the second frequency-divided clock and the fourth frequency-divided clock, . . . , the (N−1)th frequency-divided clock and the (N+1)th frequency-divided clock, and the Nth frequency-divided clock and the (N+2)th frequency-divided clock, each of the reference clocks is generated by adding together both frequency-divided clocks in each combination and dividing the sum thereof by 2; and

the phase comparison circuit detects N respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks.

5. The inter-phase skew detection circuit in accordance with claim 3 , wherein:

the phase comparison reference clock generation circuit uses a phase interpolators for generating each of the reference clocks by adding together both frequency-divided clocks in each combination and dividing the sum thereof by 2; and

the phase comparison target clock generation circuit delays said each of N frequency-divided clocks by an amount of delay corresponding to a delay time of an output signal generated in the phase interpolator.

6. An inter-phase skew adjustment circuit comprising:

the inter-phase skew detection circuit in accordance with claim 4 ; and

a phase adjustment delay circuit that adjusts each phase of the N-phase clocks input into the frequency division circuit, based on the phase comparison results obtained by the phase comparison circuit in the inter-phase skew detection circuit.

7. A semiconductor integrated circuit comprising the inter-phase skew adjustment circuit in accordance with claim 6 .

8. An inter-phase skew adjustment circuit comprising:

the inter-phase skew detection circuit in accordance with claim 1 ; and

a phase adjustment delay circuit that adjusts each phase of the N-phase clocks input into the frequency division circuit, based on the phase comparison results obtained by the phase comparison circuit in the inter-phase skew detection circuit.

9. A semiconductor integrated circuit comprising the inter-phase skew adjustment circuit in accordance with claim 8 .