Shift register
An exemplary shift register includes a control circuit and an output circuit. The control circuit is electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal. A logic low level of the first clock pulse signal is lower than a level of the power supply voltage. The output circuit is subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal. The second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.
1. A shift register comprising:
a control circuit, electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal, wherein a logic low level of the first clock pulse signal is lower than a level of the power supply voltage; and
an output circuit, subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal, wherein the second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.
2. The shift register as claimed in claim 1 , wherein the control circuit comprises:
a first control transistor, wherein the gate of the first control transistor is electrically coupled to receive the first clock pulse signal, the source/drain of the first control transistor is electrically coupled to the power supply voltage, and the drain/source of the first control transistor is electrically coupled to the gate of the first control transistor through a coupling capacitor; and
a second control transistor, wherein the gate of the second control transistor is electrically coupled to the gate of the first control transistor, the source/drain of the second control transistor is electrically coupled to the drain/source of the first control transistor and for outputting the enable signal, and the drain/source of the second control transistor is for receiving the start pulse signal.
3. The shift register as claimed in claim 1 , wherein the output circuit comprises a first output transistor, the gate of the first output transistor is for receiving the enable signal, the source/drain of the first output transistor is for outputting the gate driving signal, and the drain/source of the first output transistor is for receiving the second clock pulse signal.
4. The shift register as claimed in claim 3 , wherein the output circuit further comprises a second output transistor for generating a second start pulse signal, the gate of the second output transistor is electrically coupled to the gate of the first output transistor, the source/drain of the second output transistor is for outputting the second start pulse signal, and the drain/source of the second output transistor is electrically coupled to the source/drain or the drain/source of the first output transistor.
5. The shift register as claimed in claim 1 , further comprising:
a reset circuit, subjected to the control of the first clock pulse signal to pull a potential of a terminal of the output circuit for outputting the gate driving signal to a second power supply voltage, wherein a level of the second power supply voltage is substantially identical to the logic low level of the second clock pulse signal.