IP Library Granted Patent US 8,143,124
Granted Patent B2
US 8,143,124 · App. 12/032,599 · Granted Mar 27, 2012

Methods of making power semiconductor devices with thick bottom oxide layer

Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 8,143,124
App. No.
12/032,599
Granted
Mar 27, 2012
Kind
B2
Abstract

A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.

Claims (53)

1. A method of of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate;

etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench.

2. A method of of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a layer of pad oxide on the substrate;

depositing a thin layer of silicon nitride on the pad oxide;

performing an anisotropic etch to remove silicon nitride from horizontal surfaces leaving silicon nitride on active trench sidewalls;

depositing oxide on horizontal surfaces including the bottom of the active trench using a sub-atmospheric chemical vapor deposition process;

removing a sandwich layer of oxide-nitride-oxide from active trench sidewalls by an etch process;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench.

3. The method of claim 1 further comprising masking the charge control trench so that the charge control trench remains substantially filled with oxide.

4. A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a substantially flat layer of oxide having a target thickness at the bottom of the active trench;

lining the sidewalls of the active trench with an oxide material;

depositing a first conductive layer over the thick oxide layer on the bottom of the active trench;

depositing an inter-electrode dielectric material over the first conductive layer;

depositing a second conductive layer over the inter-electrode dielectric material; and

forming source regions having the first conductivity type in the well region adjacent the active trench.

5. A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a substantially flat layer of oxide having a target thickness at the bottom of the active trench;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench;

depositing in the charge control trench a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material;

wherein the thickness of the plurality of conductive layers inside the charge control trench vary.

6. A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a substantially flat layer of oxide having a target thickness at the bottom of the active trench;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench;

depositing in the charge control trench a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material;

wherein the thickness of a first conductive layer that is deeper inside the charge control trench is smaller than the thickness of a second conductive layer that is disposed above the first conductive layer.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
Continuity (5)
Continuation 11026276 · Dec 29, 2004
Continuation In Part 10640742 · Aug 14, 2003
Continuation In Part 10442670 · May 20, 2003
Provisional Application 60533790 · Dec 30, 2003
Related Publication 20080138953A1 · Jun 12, 2008