Current-mode gain-splitting dual-path VCO
Techniques to effectively handle large voltage-controlled oscillator (VCO) gain are described. The techniques utilize (1) a slow high-gain path to provide an average control current that adjusts the center frequency of a VCO and (2) a fast low-gain path to provide an instantaneous control current that adjusts the VCO frequency during normal operation. In one design, the VCO includes a voltage-to-current converter, a current amplifier, a summer, and a current-controlled oscillator (ICO). The voltage-to-current converter receives a control voltage and generates a first current and a second current. The current amplifier amplifies and filters the first current and generates a third current. The summer sums the second current and the third current and generates a control current. The ICO receives the control current and generates an oscillator signal having a frequency determined by the control current.
1. An integrated circuit comprising:
a voltage-to-current converter configured to receive an analog control voltage and generate both a first current and a second current based on the analog control voltage, wherein the first current is equal to the second current;
a current amplifier configured to filter and amplify the first current with a gain greater than one and generate a third current;
a summer configured to sum the second current and the third current to generate a control current; and
a current-controlled oscillator (ICO) configured to receive the control current and generate an oscillator signal having a frequency determined by the control current.
2. The integrated circuit of claim 1 , wherein the voltage-to-current converter is configured to generate the second current as a current mirror of the first current.
3. The integrated circuit of claim 1 , wherein the current amplifier comprises a current mirror configured to receive the first current and provide the third current.
4. The integrated circuit of claim 3 , wherein the current amplifier further comprises a capacitor configured to provide filtering for the first current.
5. The integrated circuit of claim 1 , wherein the summer is formed by a summing node for outputs of the voltage-to-current converter and the current amplifier.
6. The integrated circuit of claim 1 , wherein the voltage-to-current converter and the current amplifier are implemented with field effect transistors (FETs).
7. The integrated circuit of claim 1 , further comprising:
a divider configured to divide the oscillator signal in frequency and provide a feedback signal;
a phase-frequency detector configured to compare phases of the feedback signal and a reference signal and provide a detector signal; and
a loop filter configured to filter the detector signal and provide the analog control voltage.
8. The integrated circuit of claim 7 , wherein the loop filter has a first bandwidth and the current amplifier has a second bandwidth that is smaller than the first bandwidth.
9. The integrated circuit of claim 7 , wherein the phase-frequency detector comprises
a charge pump configured to receive a digital phase error signal indicative of phase error between the feedback signal and the reference signal and to provide the detector signal.
10. The integrated circuit of claim 1 , wherein the voltage-to-current converter comprises
a first transistor configured to receive the analog control voltage at a gate and provide the first current at a drain, and
a second transistor matched to the first transistor and configured to receive the analog control voltage at a gate and provide the second current at a drain.
11. The integrated circuit of claim 1 , wherein the voltage-to-current converter has a bandwidth wider than a bandwidth of the analog control voltage.
12. The integrated circuit of claim 1 , wherein the voltage-to-current converter is after a charge pump and a loop filter in a phase-locked loop.
13. The integrated circuit of claim 1 , wherein the first current changes slower than the second current and in parallel with the second current.
14. A method comprising:
generating both a first current and a second current based on an analog control voltage, wherein the first current is equal to the second current;
filtering and amplifying the first current with a gain greater than one to generate a third current;
summing the second current and the third current to generate a control current; and
generating an oscillator signal having a frequency determined by the control current.
15. The method of claim 14 , further comprising:
dividing the oscillator signal in frequency to generate a feedback signal;
comparing phases of the feedback signal and a reference signal to generate a detector signal; and
filtering the detector signal to generate the analog control voltage.
16. An apparatus comprising:
means for generating both a first current and a second current based on an analog control voltage, wherein the first current is equal to the second current;
means for filtering and amplifying the first current with a gain greater than one to generate a third current;
means for summing the second current and the third current to generate a control current; and
means for generating an oscillator signal having a frequency determined by the control current.
17. The apparatus of claim 16 , further comprising:
means for dividing the oscillator signal in frequency to generate a feedback signal;
means for comparing phases of the feedback signal and a reference signal to generate a detector signal; and
means for filtering the detector signal to generate the analog control voltage.
18. An integrated circuit comprising:
a converter configured to receive an analog control voltage, to generate a first current based on the analog control voltage, to generate a second current via a fast low-gain path based on the analog control voltage, to filter and amplify the first current with a gain greater than one to generate a third current via a slow high-gain path, and to sum the third current and the second current to generate a control current, wherein the first current is equal to the second current; and
a current-controlled oscillator (ICO) configured to receive the control current and generate an oscillator signal having a frequency determined by the control current.
19. The integrated circuit of claim 18 , wherein the slow high-gain path has a fixed gain factor of m relative to the fast low-gain path, where m is greater than one.
20. The integrated circuit of claim 18 , further comprising:
a phase-locked loop configured to receive a reference signal and the oscillator signal and to generate the analog control voltage such that the frequency of the oscillator signal is locked to a frequency of the reference signal.
21. A wireless device comprising:
a converter configured to receive an analog control voltage, to generate a first current based on the analog control voltage, to generate a second current via a fast low-gain path based on the analog control voltage, to filter and amplify the first current with a gain greater than one to generate a third current via a slow high-gain path, and to sum the third current and the second current to generate a control current, wherein the first current is equal to the second current; and
a current-controlled oscillator (ICO) configured to receive the control current and generate an oscillator signal having a frequency determined by the control current.
22. The wireless device of claim 21 , wherein the slow high-gain path has a fixed gain factor of m relative to the fast low-gain path, where m is greater than one.
23. The wireless device of claim 21 , further comprising:
a phase-locked loop configured to receive a reference signal and the oscillator signal and to generate the analog control voltage such that the frequency of the oscillator signal is locked to a frequency of the reference signal.
24. The wireless device of claim 21 , wherein the oscillator signal is used to generate clock signals for digital circuitry.
25. The wireless device of claim 21 , wherein the oscillator signal is used for frequency upconversion in a transmitter or frequency downconversion in a receiver.