IP Library › Granted Patent US 8,145,820
Granted Patent B2
US 8,145,820 · App. 12/614,046 · Granted Mar 27, 2012

Multiprocessor system and computer program product

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,145,820
App. No.
12/614,046
Granted
Mar 27, 2012
Kind
B2
Abstract

In a multiprocessor system including a plurality of processors, the processors execute, at a time of migration a task operating in own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and when an interrupt request to be received and executed by an interrupt handler accompanying the migration target task is generated during transmission of the migration target task, the transmitting task receives the interrupt request instead of the interrupt handler and starts the interrupt handler.

Claims (26)

1. A multiprocessor system comprising a plurality of processors, wherein

the processors execute, at a time of migrating a task running on own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and

when an interrupt request to be received and handled by an interrupt handler accompanying the migration target task is generated during transmission of the migration target task, the transmitting task receives the interrupt request instead of the interrupt handler and starts the interrupt handler, wherein

the destination processor executes a receiving task for receiving the migration target task,

the receiving task obtains an interrupt handle permission to perform an interrupt handler accompanying the migration target task, which is obtained by only one of the own processor and a source processor of the migration target task, and after completion of reception of the migration target task by the own processor, deletes the migration target task from the source processor and discards the interrupt handle permission, and

upon reception of the interrupt request, a transmitting task being executed by the source processor attempts to obtain the interrupt handle permission, and when the interrupt handle permission is obtained, starts an interrupt handler accompanying the migration target task.

2. The multiprocessor system according to claim 1 , further comprising a storage unit that is readable and writable by the processors, wherein

the storage unit stores interrupt handle permission information that indicates a processor that has the interrupt handle permission, among the processors.

3. The multiprocessor system according to claim 1 , wherein

the processors include a processor that executes a migration instruction task for generating migration control information in which a migration target task and a destination processor of the migration target task are specified, and

a transmitting task being executed by a source processor of the migration target task transmits the migration target task based on the migration control information.

4. The multiprocessor system according to claim 3 , further comprising a storage unit that is readable and writable by the processors, wherein

the storage unit stores the migration control information.

5. The multiprocessor system according to claim 3 , wherein when there is a processor that is executing tasks of a number exceeding a predetermined number, the task operating in the processor is specified as a migration target task, and a processor, in which a number of tasks being executed does not exceed the predetermined number even if the migration target task is added thereto, is specified as a destination processor.

6. The multiprocessor system according to claim 3 , wherein when a total number of tasks being executed by the processors reaches a state that can be executed by a fewer number of processors, the migration instruction task generates migration control information specifying all the tasks being executed by a processor having a smallest number of tasks being executed as migration target tasks.

7. The multiprocessor system according to claim 5 , wherein the migration instruction task causes a processor that is executing the migration target task to start the transmitting task.

8. The multiprocessor system according to claim 6 , wherein the migration instruction task causes a processor that is executing the migration target task to start the transmitting task.

9. A non-transitory tangible medium comprising a plurality of commands executable by a computer including a plurality of processors, wherein

at a time of migrating a task running on own processor to another processor, when an interrupt request to be received and handled by an interrupt handler accompanying the migration target task occurs during transmission of the migration target task, the commands cause each of the processors to receive the interrupt request instead of the interrupt handler and start the interrupt handler, wherein

the commands further cause each of the processors to:

obtain an interrupt handle permission to perform an interrupt handling accompanying the migration target task, which is by only one of the own processor and a source processor of the migration target task, at the time of receiving the migration target task; and

delete the migration target task from the source processor and discard the interrupt handle permission, after completion of reception of the migration target task by the own processor.

10. The medium according to claim 9 , wherein

the commands further causes each of the processors to:

attempt to obtain the interrupt handle permission when the interrupt request is received during transmission of the migration target task; and

start an interrupt handler accompanying the migration target task when the interrupt handle permission is ensured.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2009
From: TANAKA, HIROAKI; KODAKA, TAKESHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023647/0185 →
Priority Claims (1)
JP 2009-125591 · May 25, 2009 · national
Continuity (1)
Related Publication 20100299472A1 · Nov 25, 2010