IP Library Granted Patent US 8,148,789
Granted Patent B2
US 8,148,789 · App. 12/260,589 · Granted Apr 3, 2012

Non-volatile semiconductor storage device and method of manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,148,789
App. No.
12/260,589
Granted
Apr 3, 2012
Kind
B2
Abstract

A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.

Claims (29)

1. A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, and a selection gate transistor controlling whether to conduct current to the memory strings, wherein

each of the memory strings comprises:

a first columnar semiconductor layer extending in a direction perpendicular to a substrate;

a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges;

a block insulation layer contacting the charge accumulation layer;

a plurality of first conductive layers contacting the block insulation layer; and

a first sealing/insulating layer formed to seal the top of the space made by the first air gap,

the charge accumulation layer being continuously formed over the plurality of memory cells,

the selection gate transistor comprises:

a second columnar semiconductor layer formed in contact with the top or bottom surface of the first columnar semiconductor layer and extending in a direction perpendicular to the substrate; and

a second conductive layer formed along the second columnar semiconductor layer,

the first sealing/insulating layer is formed in a position different from a position between the second columnar semiconductor layer and the second conductive layer.

2. The non-volatile semiconductor storage device according to claim 1 ,

the second conductive layer is formed on the second columnar semiconductor layer via a second air gap.

3. The non-volatile semiconductor storage device according to claim 2 , wherein

the selection gate transistor further comprises a second sealing/insulating layer formed to seal the top of the space made by the second air gap.

4. The non-volatile semiconductor storage device according to claim 1 ,

a gate insulation layer contacting the second columnar semiconductor layer, the second conductive layer is contacting the gate insulation layer, and the gate insulation layer has a second air gap or a seam.

5. A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, and a selection gate transistor controlling whether to conduct current to the memory strings, wherein

each of the memory strings comprises,

a first columnar semiconductor layer extending in a direction perpendicular to a substrate,

a charge accumulation layer formed around the first columnar semiconductor layer and accumulating charges,

a block insulation layer contacting the charge accumulation layer, and

a plurality of first conductive layers contacting the block insulation layer,

the charge accumulation layer being continuously formed over the plurality of memory cells; and

the selection gate transistor comprises,

a second columnar semiconductor layer extending in a direction perpendicular to a substrate, and

a second conductive layer formed on the second columnar semiconductor layer via a second air gap; and

a second sealing/insulating layer configured to seal the top of the space made by the second air gap and formed in a position different from a position between the first columnar semiconductor layer and the first conductive layer.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2008
From: KITO, MASARU; KATSUMATA, RYOTA; KIDOH, MASARU; TANAKA, HIROYASU; FUKUZUMI, YOSHIAKI; AOCHI, HIDEAKI; MATSUOKA, YASUYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 021964/0121 →
Priority Claims (1)
JP 2007-280091 · Oct 29, 2007 · national
Continuity (1)
Related Publication 20090108333A1 · Apr 30, 2009