Clock duty correction circuit

1. A clock duty correction circuit comprising:

a first current sourcing unit configured to source a current to a current path in response to a clock signal;

a first current sinking unit configured to sink the current of the current path in response to the clock signal;

a second current sourcing unit configured to source a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time;

a second current sinking unit configured to sink the current of the current path in response to the delay clock signal;

a current adjustment unit configured to adjust an amount of the current flowing through the current path according to a voltage level of a control voltage; and

a clock output unit configured to output an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit.

2. The clock duty correction circuit according to claim 1 , further comprising a delay unit configured to delay the clock signal by a predetermined delay value to output the delay clock signal.

3. The clock duty correction circuit according to claim 1 , further comprising a control voltage generation unit configured to generate the control voltage having a voltage level corresponding to a code value of a duty control code.

4. The clock duty correction circuit according to claim 3 , further comprising a duty control code output unit which is configured to output the duty control codes.

5. The clock duty correction circuit according to claim 4 , wherein the duty control code output unit comprises a latch section which is configured to store the duty control codes.

6. The clock duty correction circuit according to claim 3 , wherein the duty control codes are transmitted from a mode register set.

7. The clock duty correction circuit according to claim 3 , wherein the control voltage generation unit comprises:

a first voltage drop element group coupled between a supply voltage terminal and a control voltage output terminal;

a second voltage drop element group coupled between a ground voltage terminal and the control voltage output terminal; and

a distribution adjustment section configured to adjust a voltage distribution ratio between the first voltage drop element group and the second voltage drop element group according to the code values of the duty control codes.

8. The clock duty correction circuit according to claim 7 , wherein the distribution adjustment section comprises a plurality of switching elements controlled by the duty control codes.

9. The clock duty correction circuit according to claim 7 , wherein the voltage level of the voltage control is determined by the voltage distribution ratio.

10. The clock duty correction circuit according to claim 3 , wherein the first current sourcing unit comprises a first sourcing transistor which is coupled between a supply voltage terminal and a first node and controlled by the clock signal.

11. The clock duty correction circuit according to claim 10 , wherein the second current sourcing unit comprises a second sourcing transistor which is coupled between the supply voltage terminal and the first node and controlled by the delay clock signal.

12. The clock duty correction circuit according to claim 11 , wherein the first current sinking unit comprises a first sinking transistor which is coupled between a ground voltage terminal and a second node and controlled by the clock signal.

13. The clock duty correction circuit according to claim 12 , wherein the second current sinking unit comprises a second sinking transistor which is coupled between the ground voltage terminal and the second node and controlled by the delay clock signal.

14. The clock duty correction circuit according to claim 13 , wherein the current adjustment unit comprises a transistor which is coupled between the first node and the second node and controlled by the control voltage.

15. The clock duty correction circuit according to claim 14 , wherein the clock output unit comprises a buffering section which is configured to buffer a signal outputted from the first node to output the output clock signal.

16. The clock duty correction circuit according to claim 1 , wherein the first current sourcing unit comprises a first sourcing transistor, which is coupled between a supply voltage terminal and a first node and controlled by the clock signal.

17. The clock duty correction circuit according to claim 16 , wherein the second current sourcing unit comprises a second sourcing transistor which is coupled between the supply voltage terminal and the first node and controlled by the delay clock signal.

18. The clock duty correction circuit according to claim 17 , wherein the first current sinking unit comprises a first sinking transistor which is coupled between a ground voltage terminal and a second node and controlled by the clock signal.

19. The clock duty correction circuit according to claim 18 , wherein the second current sinking unit comprises a second sinking transistor which is coupled between the ground voltage terminal and the second node and controlled by the delay clock signal.

20. The clock duty correction circuit according to claim 19 , wherein the current adjustment unit comprises a transistor which is coupled between the first node and the second node and controlled by the control voltage.

21. The clock duty correction circuit according to claim 20 , wherein the clock output unit comprises a buffering section which is configured to buffer a signal outputted from the first node to output the output clock signal.