Data encryption and decryption with a key by an N-state inverter modified switching function
Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.
1. A method for deciphering a plurality of n-state symbols with n>2, comprising:
receiving by a processor on a first input of an implementation of a first n-state switching function a signal representing an n-state symbol in a codeword of n-state symbols, wherein the n-state switching function is determined by an n by n truth table that does not represent an addition over an n-state finite field GF(n);
receiving by the processor on a second input of the implementation of the first n-state switching function a signal representing a first n-state key symbol; and
providing by the processor on an output of the implementation of the first n-state switching function a signal representing an intermediate deciphered n-state symbol.
2. The method of claim 1 , further comprising:
receiving by the processor on a first input of an implementation of a second n-state switching function a signal representing a second n-state symbol in a codeword of n-state symbols;
receiving by the processor on a second input of the implementation of the second n-state switching function a signal representing a second n-state key symbol;
providing by the processor on an output of the implementation of the second n-state switching function a signal representing a transitional n-state symbol; and
inputting by the processor the intermediate deciphered n-state symbol and the transitional n-state symbol on a first and a second input of an implementation of the first n-state switching function to generate a deciphered n-state symbol.
3. The method of claim 1 , wherein the n by n truth table is a non-commutative truth table.
4. The method of claim 1 , wherein the n by n truth table is a commutative truth table that is modified in accordance with an n-state inverter.
5. The method of claim 1 , wherein the n by n truth table is implemented on a memory.
6. The method of claim 1 , wherein the n by n truth table is implemented on the processor by a combination of an implementation of an n-state inverter and an implementation of an addition over GF(n).
7. The method of claim 1 , wherein an n-state symbol is represented by one or more binary signals.
8. The method of claim 1 , wherein the method is applied in a communication system.
9. The method of claim 1 , wherein the method is applied in a financial system.
10. The method of claim 1 , wherein the method is applied in a data storage system.
11. An apparatus to decipher a plurality of n-state symbols with n>2, comprising:
a processor enabled to execute instruction to perform the steps:
receiving on a first input of an implementation of a first n-state switching function a signal representing a first enciphered n-state symbol in a codeword of n-state symbols, wherein the n-state switching function is determined by an n by n truth table that does not represent an addition over an n-state finite field GF(n);
receiving on a second input of the implementation of the first n-state switching function a signal representing a first n-state key symbol; and
providing on an output of the implementation of the first n-state switching function a signal representing an intermediate deciphered n-state symbol.
12. The apparatus of claim 11 , the processor further executing instructions to perform the steps:
receiving on a first input of an implementation of a second n-state switching function a signal representing a second enciphered n-state symbol in the codeword of n-state symbols;
receiving on a second input of the implementation of the second n-state switching function a signal representing a second n-state key symbol;
providing on an output of the implementation of the second n-state switching function a signal representing a transitional n-state symbol; and
inputting the intermediate deciphered n-state symbol and the transitional n-state symbol on a first and a second input of an implementation of the first n-state switching function to generate a deciphered n-state symbol.
13. The apparatus of claim 11 , wherein the n by n truth table is a non-commutative truth table.
14. The apparatus of claim 11 , wherein the n by n truth table is a commutative truth table that is modified in accordance with an n-state inverter.
15. The apparatus of claim 11 , wherein the processor is implemented on a field programmable gate array.
16. The apparatus of claim 11 , wherein the n by n truth table is implemented by a combination of an implementation of an n-state inverter and an implementation of an addition over GF(n).
17. The apparatus of claim 11 , wherein an n-state symbol is represented by one or more binary signals.
18. The apparatus of claim 11 , wherein the apparatus is part of a communication system.
19. The apparatus of claim 11 , wherein the apparatus is part of a financial system.
20. The apparatus of claim 11 , wherein the apparatus is part of a data storage system.