Interposer and electronic device using the same
Means for Solution: This interposer ( 10 ) comprises the silicon substrate ( 12 ), a plurality of through-hole conductors ( 20 ) formed on the above-described silicon substrate, and a capacitor ( 15 ) formed with the upper electrodes ( 14 ) and the lower electrodes ( 18 ) formed by extending the land portions of the above-described through-hole conductors and the dielectric layer ( 16 ) formed between the both electrodes. The rewiring layers ( 23 - 1, 23 - 2 ) formed as desired are formed on the layers other than the above-described capacitor layer.
1. An interposer comprising:
a silicon substrate having a polished surface and a plurality of through holes;
a capacitor formed on substantially an entire face of the polished surface of the silicon substrate, the capacitor comprising a lower electrode formed on the polished surface of the silicon substrate, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer,
a plurality of through-hole conductors formed through the silicon substrate and electrically connected to the capacitor, the plurality of through-hole conductors comprising a through-hole conductor for signal, a through-hole conductor for power supply, and a through-hole conductor for ground,
a plurality of through-hole lands which are formed on the polished surface of the silicon substrate and comprise a through-hole land for signal and a through-hole land for ground;
a plurality of via conductors which are formed through the dielectric layer and comprise a via conductor for signal, a via conductor for power supply, and a via conductur for ground; and
a plurality of via lands which are formed on the dielectric layer and comprise a via land for signal and a via land for power supply,
wherein the through-hole conductor for signal is electrically connected to the through-hole land for signal, to the via conductor for signal, and to the via land for signal, the through-hole land for signal is electrically insulated from the lower electrode by a first clearance, the via land for signal is electrically insulated from the upper electrode by a second clearance,
the through-hole conductor for power supply is electrically connected to the lower electrode, to the via conductor for power supply, and to the via land for power supply the via land for power supply is electrically insulated from the upper electrode by the second clearance,
the through-hole conductor for ground is electrically connected to the through-hole land for ground, to the via conductor for ground, and to the upper electrode, and the through-hole land for ground is electrically insulated from the lower electrode by the first clearance.
2. The interposer as set forth in claim 1 , wherein the through-hole conductor for power supply and the through-hole conductor for ground are formed in a central region of the silicon substrate, and the through-hole conductor for signal is formed in a peripheral region of the silicon substrate.
3. The interposer as set forth in claim 1 , wherein the through-hole conductors and the via conductors are made of copper.
4. The interposer as set forth in claim 1 , wherein the upper electrode and the lower electrode are made of nickel or platinum.
5. The interposer as set forth in claim 1 , wherein the dielectric layer is made of a ferroelectric substance.
6. The interposer as set forth in claim 1 , wherein the dielectric layer is made of barium titanate.
7. The interposer as set forth in claim 1 , further comprising a solder resist layer or an insulating resin layer which covers at least one face of the interposer.
8. The interposer as set forth in claim 1 , wherein the upper electrode is part of a plane layer having an opening portion formed therein such that a clearance is formed between the upper electrode and an adjacent conductor, and the lower electrode is part of a plane layer having an opening portion formed therein such that a clearance is formed between the lower electrode and an adjacent conductor.
9. An electronic device comprising:
an IC chip;
a package substrate; and
the interposer as set forth in claim 1 ,
wherein the interposer is interposed between the IC chip and the package substrate and electrically connected to each of the IC chip and the package substrate.
10. The interposer as set forth in claim 1 , wherein the through-hole conductor for power supply and the through-hole conductor for ground are formed in a peripheral region of the silicon substrate, and the through-hole conductor for signal is formed in a central region of the silicon substrate.
11. An interposer comprising:
a silicon substrate having a polished surface and a plurality of through holes;
a capacitor formed on substantially an entire face of the polished surface of the silicon substrate the capacitor comprising a lower electrode formed on the polished surface of the silicon substrate, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer;
a plurality of through-hole conductors formed through the silicon substrate and electrically connected to the capacitor, the plurality of through-hole conductors comprising a through-hole conductor for signal, a through-hole conductor for power supply, and a through-hole conductor for ground;
a plurality of through-hole lands which are formed on the polished surface of the silicon substrate and comprise a through-hole land for signal and a through-hole land for power supply;
a plurality of via conductors which are formed through the dielectric layer and comprise a via conductor for signal, a via conductor for power supply, and a via conductor for ground; and
a plurality of via lands which are formed on the dielectric layer and comprise a via land for signal and a via land for ground,
wherein the through-hole conductor for power supply is electrically connected to the through-hole land for power supply, to the via conductor for power supply, and to the upper electrode, the through-hole land for power supply is electrically insulated from the lower electrode by a first clearance,
the through-hole conductor for signal is electrically connected to the through-hole land for signal, to the via conductor for signal, and to the via land for signal, the through-hole land for signal is electrically insulated from the lower electrode by the first clearance, the via land for signal is electrically insulated from the upper electrode by a second clearance,
the through-hole conductor for ground is electrically connected to the lower electrode, to the via conductor for ground, and to the via land for ground, and the via land for ground is electrically insulated from the upper by the second clearance.
12. The interposer as set forth in claim 11 , wherein the through-hole conductor for power supply and the through-hole conductor for ground are formed in a central region of the silicon substrate, and the through-hole conductor for signal is formed in a peripheral region of the silicon substrate.
13. The interposer as set forth in claim 11 , wherein the through-hole conductor for power supply and the through-hole conductor for ground are formed in a peripheral region of the silicon substrate, and the through-hole conductor for signal is formed in a central region of the silicon substrate.
14. The interposer as set forth in claim 11 , wherein the through-hole conductors and the via conductors are made of copper.
15. The interposer as set forth in claim 11 , wherein the upper electrode and the lower electrode are made of nickel or platinum.
16. The interposer as set forth in claim 11 , wherein the dielectric layer is made of a ferroelectric substance.
17. The interposer as set forth in claim 11 , wherein the dielectric layer is made of barium titanate.
18. The interposer as set forth in claim 11 , further comprising a solder resist layer or an insulating resin layer which covers at least one face of the interposer.
19. The interposer as set forth in claim 11 , wherein the lower electrode is part of a plane layer having an opening portion formed therein such that a clearance is formed between the lower electrode and an adjacent conductor, and the upper electrode is part of a plane layer having an opening portion formed therein such that a clearance is formed between the upper electrode and an adjacent conductor.
20. An electronic device comprising:
an IC chip;
a package substrate; and
the interposer as set forth in claim 11 ,
wherein the interposer is interposed between the IC chip and the package substrate and electrically connected to each of the IC chip and the package substrate.