Semiconductor memory devices including a vertical channel transistor having a buried bit line

1. A semiconductor memory device of comprising:

a semiconductor substrate including a plurality of pillars separated from each other by a predetermined distance;

a device isolation film between the pillars;

respective surrounding gate electrodes electrically insulated from the pillars and surrounding an upper outside of each pillar;

first source/drain regions formed in an upper portion of respective ones of the pillar;

a second source/drain region formed in the semiconductor substrate between adjacent ones of the pillars;

a buried bit line, interposed between the second source/drain region and the device isolation film, electrically contacting the second source/drain region;

a word line formed in a cross-wise pattern with the bit line and electrically connected to ones of the surrounding gate electrodes;

contact pads, formed on respective ones of the first source/drain regions and contacting the respective ones of the first source/drain regions;

storage node electrodes formed on the contact pads; and

conductive spacers between an upper outside of the surrounding gate electrodes and the word line.

2. The semiconductor memory device of claim 1 , wherein a conductive film for the conductive spacers and the word line is a transition metal film formed of tungsten (W), cobalt (Co), nickel (Ni), and/or titanium (Ti); a transition metal silicide film formed of tungsten silicide (WSi x ), cobalt silicide (CoSi x ), nickel silicide (NiSi x ), and/or titanium silicide (TiSi x ); and/or a tungsten nitride film (WN)/tungsten film (W).

3. The semiconductor memory device of claim 1 , wherein the bit line surrounds a lower outside of respective ones of the pillars.

4. The semiconductor memory device of claim 1 , wherein the bit line is a transition metal silicide film.

5. A semiconductor memory device comprising:

a semiconductor substrate;

a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate;

respective surrounding gate electrodes surrounding ones of the pillars;

a first source/drain region in the semiconductor substrate between adjacent ones of the pillars;

a second source/drain region in an upper portion of at least one of the adjacent pillars;

a buried bit line in the first source/drain region and electrically coupled to the first source/drain region;

a storage node electrode on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region;

a word line contacting with ones of the surrounding gate electrodes and extending in a cross-wise pattern relative to the bit line; and

respective conductive spacers between the word line and the ones of the surrounding gate electrodes contacting the word line.

6. The semiconductor memory device of claim 5 , wherein the conductive spacers are on an upper outside surface of the surrounding gate electrodes.

7. The semiconductor memory device of claim 5 , wherein a conductive film for the conductive spacers and the word line comprises a transition metal film of tungsten (W), cobalt (Co), nickel (Ni), and/or titanium (Ti); a transition metal silicide film of tungsten silicide (WSi x ), cobalt silicide (CoSi x ), nickel silicide (NiSi x ), and/or titanium silicide (TiSi x ); and/or a tungsten nitride film (WN)/tungsten film (W).

8. The semiconductor memory device of claim 5 , wherein the first and second source/drain regions are electrically insulated from the surrounding gate electrodes.

9. The semiconductor memory device of claim 5 , wherein a dielectric material is located between adjacent ones of the pillars to electrically insulate the adjacent ones of the pillars.

10. The semiconductor memory device of claim 5 , wherein the bit line is a transition metal silicide film.

11. The semiconductor memory device of claim 5 wherein:

the plurality of pillars are formed in a matrix and are separated from each other by a predetermined distance;

the first source/drain region is a drain region of a vertical channel transistor; and

the second source/drain region is a source region of the vertical channel transistor.