Memory device with error correction capability and efficient partial word write operation
A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.
1. A memory device comprising:
a memory array having a plurality of memory cells configured to store data;
said memory device being configured at least to perform a partial word write operation and a read operation, the partial word write operation comprising a read phase and a write phase, wherein the write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation;
wherein bitlines of said memory array are time multiplexed within said clock cycle between the write phase of the partial word write operation and the read operation.
2. The memory device of claim 1 wherein the partial word write operation comprises at least one of a byte write operation and a bit write operation.
3. The memory device of claim 1 wherein the write phase of the partial word write operation occurs substantially simultaneously with the read operation.
4. The memory device of claim 1 wherein the read operation comprises a read phase of another partial word write operation.
5. The memory device of claim 1 wherein during a first portion of said clock cycle, write data to be written to a first one of the memory cells as part of the partial word write operation is carried by a given bitline of the memory array, and during a second portion of the clock cycle, read data read from a second one of the memory cells as part of the read operation is also carried by the given bitline.
6. The memory device of claim 1 wherein the memory cells are arranged in a plurality of sub-blocks having respective sets of local bitlines, said local bitlines being coupled to a set of global bitlines shared by the plurality of sub-blocks.
7. The memory device of claim 6 wherein the global bitlines are time multiplexed within said clock cycle between the write phase of the partial word write operation and the read operation.
8. The memory device of claim 7 wherein the time multiplexing of the global bitlines is configured such that in said clock cycle the global bitlines are first utilized to move write data from a data input to a first set of local sense amplifiers, coupled to respective ones of a first set of local bitlines of a first one of the sub-blocks, for latching as part of the write phase of the partial word write operation, and after the write data is latched in the first set of local sense amplifiers, the global bitlines are then utilized to move read data previously latched in a second set of local sense amplifiers, coupled to respective ones of a second set of local bit lines of a second one of the sub-blocks, to the error correction circuitry as part of the read operation.
9. The memory device of claim 6 wherein during a first portion of said clock cycle the global bitlines are dedicated for use with write data for the partial word write operation, and wherein during a second portion of the clock cycle the global bitlines are dedicated for use with read data for the read operation.
10. The memory device of claim 1 wherein the memory device comprises a stand-alone memory device.
11. The memory device of claim 1 wherein the memory device comprises an embedded memory device.
12. The memory device of claim 1 , further comprising error correction circuitry coupled to the memory array and configured to process data retrieved from the memory array to generate corrected data.
13. An integrated circuit comprising:
a memory device; and
additional circuitry coupled to the memory device,
said memory device comprising:
a memory array having a plurality of memory cells configured to store data;
said memory device being configured at least to perform a partial word write operation and a read operation, the partial word write operation comprising a read phase and a write phase, wherein the write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation;
wherein bitlines of said memory array are time multiplexed within said clock cycle between the write phase of the partial word write operation and the read operation.
14. The integrated circuit of claim 13 wherein said additional circuitry comprises a processor.
15. The integrated circuit of claim 13 wherein during a first portion of said clock cycle, write data to be written to a first one of the memory cells as part of the partial word write operation is carried by a given bitline of the memory array, and during a second portion of the clock cycle, read data read from a second one of the memory cells as part of the read operation is also carried by the given bitline.
16. The integrated circuit of claim 13 , wherein the memory device further comprises error correction circuitry coupled to the memory array and configured to process data retrieved from the memory array to generate corrected data.
17. A method for performing operations in a memory device comprising a memory array having a plurality of memory cells configured to store data, the method comprising the steps of:
performing a partial word write operation comprising a read phase and a write phase; and
performing a read operation;
wherein the write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation; and
wherein the performing steps further comprise the step of time multiplexing bitlines of said memory array within said clock cycle between the write phase of the partial word write operation and the read operation.
18. The method of claim 17 wherein during a first portion of said clock cycle, write data to be written to a first one of the memory cells as part of the partial word write operation is carried by a given bitline of the memory array, and during a second portion of the clock cycle, read data read from a second one of the memory cells as part of the read operation is also carried by the given bitline.
19. The method of claim 17 wherein the memory cells are arranged in a plurality of sub-blocks having respective sets of local bitlines, said local bitlines being coupled to a set of global bitlines shared by the plurality of sub-blocks, and further wherein the global bitlines are time multiplexed within said clock cycle between the write phase of the partial word write operation and the read operation.
20. The method of claim 17 , wherein the memory device further comprises error correction circuitry coupled to the memory array and configured to process data retrieved from the memory array to generate corrected data.
21. A memory device comprising:
a memory array having a plurality of memory cells configured to store data;
said memory device being configured to perform at least a write operation and a read operation;
wherein the memory device comprises a plurality of bitlines associated with the memory cells of the array, at least a given one of said bitlines being used to transfer write data during one portion of a given clock cycle of the memory device and at least the given one of said bitlines being used to transfer read data during a different portion of the given clock cycle;
wherein the write operation comprises a partial word write operation; and
wherein the partial word write operation comprises a read phase and a write phase, and wherein the plurality of bitlines are time multiplexed within the given clock cycle between the write phase of the partial word write operation and the read operation.
22. The memory device of claim 21 wherein the plurality of bitlines are time multiplexed within the given clock cycle between the write operation and the read operation.
23. A method for performing operations in a memory device comprising a memory array having a plurality of memory cells configured to store data, said memory device being configured to perform at least a write operation and a read operation, the method comprising the steps of:
utilizing at least a given one of a plurality of bitlines associated with the memory cells of the array to transfer write data during one portion of a given clock cycle of the memory device; and
utilizing at least the given one of said plurality of bitlines to transfer read data during a different portion of the given clock cycle;
wherein the write operation comprises a partial word write operation;
wherein the partial word write operation comprises a read phase and a write phase, and wherein the utilizing steps further comprise the step of time multiplexing the plurality of bitlines within the given clock cycle between the write phase of the partial word write operation and the read operation.
24. The method of claim 23 wherein the utilizing steps further comprise the step of time multiplexing the plurality of bitlines within the given clock cycle between the write operation and the read operation.