Heating center PCRAM structure and methods for making
Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater material is on the first phase change material. A second phase change layer comprising a second phase change material is on the resistive heater, and a top electrode is on the second phase change layer. The heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials.
1. A memory device comprising:
a dielectric layer having a top surface;
a via extending from the top surface of the dielectric layer and having a bottom portion and a top portion;
a bottom electrode within the bottom portion of the via;
a first phase change layer comprising a first phase change material within the top portion of the via and contacting the bottom electrode, the first phase change layer having a first contact area on a top surface having a first width;
a resistive heater layer comprising a heater material having a bottom side in contact with the contact surface on the first phase change layer and having a second contact area on a top side, the second contact area having a second width greater than the first width, and wherein the resistive heater layer has a thickness less than or equal to 10 nm;
a second phase change layer comprising a second phase change material, the second phase change layer having a bottom side in contact with the second contact area on the top side of the resistive heater layer; and
a top electrode on the second phase change layer;
wherein the heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials.
2. The device of claim 1 , wherein the first width is less than a minimum feature size for a lithographic process used to form the memory device.
3. The device of claim 2 , wherein the resistive heater layer, second phase change layer, and top electrode form a multi-layer stack having said second width overlying the top surface of the dielectric layer.
4. The device of claim 1 , wherein the heater material has a resistivity between about 1.5 and 100 times greater than the most highly resistive states of the first and second phase change materials.
5. The device of claim 4 , wherein the heater material has a resistivity between about 4 and 50 times greater than the most highly resistive states of the first and second phase change materials.
6. The device of claim 1 , wherein the heater material comprises one of TiN, TaN, TiW, TiSiN, or TaSiN doped with carbon.
7. The device of claim 1 , wherein the first and second phase change materials comprise the same phase change material.
8. The device of claim 1 , wherein the first and second phase change materials comprise different phase change material.
9. The device of claim 1 , wherein each of the first and second phase change materials comprise a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, Si, O, P, As, N and Au.
10. A method for manufacturing a memory device, the method comprising:
providing a bottom electrode extending to a top surface of a dielectric layer;
removing a portion of the bottom electrode to form a recess;
filling the recess with a first phase change material layer to form a phase change element having a first contact area on a top side, the first contact surface having a first width;
forming a layer of heater material having a bottom side in contact with the first contact area on the first phase change layer and having a second contact area on a top side, the second contact area having a second width greater than the first width, wherein the layer of heater material has a thickness less than or equal to 10 nm;
forming a second phase change material layer having a bottom side in contact with the second contact area across said second width on the top side of the layer of heater material; and
forming a top electrode material layer on the second phase change layer;
wherein the heater material has a resistivity greater than the most highly resistive state of the first and second phase change materials.
11. The method of claim 10 , wherein the filling the recess step comprises:
forming the first phase change material layer in the recess and on the top surface of the dielectric layer; and
planarizing the first phase change material layer to expose the top surface of the dielectric layer.
12. The method of claim 11 , further comprising etching the layer of heater material, the second phase change material layer, and the top electrode material layer, thereby forming a multi-layer stack having said second width overlying the top surface of the dielectric layer.
13. The method of claim 10 , wherein the first width is less than a minimum feature size for a lithographic process used to form the memory device.
14. The method of claim 10 , wherein the heater material has a resistivity between about 1.5 and 100 times greater than the most highly resistive states of the first and second phase change materials.
15. The method of claim 10 , wherein the heater material comprises one of TiN, TaN, TiW, TiSiN, or TaSiN doped with carbon.
16. The method of claim 10 , wherein the first and second phase change materials comprise the same phase change material.
17. The method of claim 10 , wherein the first and second phase change materials comprise different phase change material.
18. The method of claim 10 , wherein each of the first and second phase change materials comprise a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, Si, O, P, As, N and Au.