III-nitride wafer and devices formed in a III-nitride wafer
A III-nitride device having a support substrate that may include a first silicon body, a second silicon body, an insulation body interposed between the first and second silicon bodies, and a III-nitride body formed over the second silicon body.
1. A semiconductor device, comprising:
a support substrate that includes a first silicon body, a second silicon body and an insulation body interposed between said first silicon body and said second silicon body; and
a III-nitride body formed over said second silicon body;
wherein said first silicon body is doped with impurities to utilize a RESURF effect.
2. The device of claim 1 , wherein said III-nitride body includes a III-nitride heterojunction comprised of a first III-nitride layer of one band gap and a second III-nitride layer of another band gap formed over said first III-nitride layer.
3. The device of claim 2 , wherein said III-nitride body includes a buffer layer interposed between said III-nitride heterojunction and said second silicon body.
4. The device of claim 1 , wherein said second silicon body is comprised of (111) silicon.
5. The device of claim 4 , wherein said first silicon body is comprised of (111) silicon.
6. The device of claim 4 , wherein said first silicon body is comprised of (100) silicon.
7. The device of claim 1 , wherein said insulation body is comprised of silicon dioxide.
8. The device of claim 1 , wherein said insulation body is between 0.1 to 2 microns thick.
9. The device of claim 1 , wherein said insulation body is about 0.5 microns thick.
10. The device of claim 1 , wherein said insulation body binds said first silicon body to said second silicon body.
11. The device of claim 1 , wherein said first silicon body is N++ doped.
12. The device of claim 1 , wherein said first silicon body is P++ doped.
13. The device of claim 1 , wherein said second silicon body includes an epitaxially formed portion.
14. The device of claim 1 , further comprising power electrodes formed over said III-nitride body.
15. The device of claim 14 , further comprising a gate arrangement disposed over said III-nitride body between respective power electrodes.
16. The device of claim 15 , wherein said gate arrangement includes a gate dielectric and a gate electrode.
17. The device of claim 15 , wherein said III-nitride body includes a III-nitride heterojunction having a two dimensional electron gas that includes interrupted regions directly under said gate arrangement.