Reset mechanism conversion
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.
1. A method comprising:
identifying, from a synchronous circuit design, each of a plurality of synchronous state holding blocks that includes a reset signal;
converting, using one or more processors, each of the plurality of synchronous state holding blocks to a corresponding asynchronous dataflow logic block that includes a reset input to generate an asynchronous circuit design that is equivalent to the synchronous circuit design; and
distributing to a location of the asynchronous dataflow logic block a replicated reset token, an operational frequency of the replicated reset token being a fraction of an operational frequency of the reset signal.
2. The method of claim 1 , wherein the identifying further comprises:
identifying at least one of the plurality of synchronous state holding blocks that includes an asynchronous reset signal.
3. The method of claim 2 , further comprising converting an operational frequency of the asynchronous reset signal to an operational frequency of a clock domain corresponding to the at least one of the plurality of synchronous state holding blocks.
4. The method of claim 1 , further comprising:
upsampling the replicated reset token at the location of the asynchronous dataflow logic block; and
providing, at the reset input of the asynchronous dataflow logic block, an upsampled reset token.
5. The method of claim 4 , wherein the providing of the upsampled reset token comprises:
providing the upsampled reset token at an operational frequency substantially the same as the operational frequency of the reset signal.
6. The method of claim 1 , wherein the distributing of the replicated reset token comprises:
distributing the replicated reset token to operate at a fraction of the operational frequency of the reset signal, the fraction being at least one of a fixed or a programmable variable.
7. The method of claim 1 , wherein the converting comprises:
converting each of the plurality of synchronous state holding blocks to at least one modified initial block that includes at least one of an upsampler or a local reset value register that operates to store a reset value corresponding to a current value of the replicated reset token.
8. The method of claim 1 , wherein the reset input comprise:
a signal that is same as the reset signal.
9. The method of claim 1 , wherein the distributing comprises:
reducing an operation frequency of the reset input by a fixed or a programmable factor to generate the replicated reset token.
10. A system comprising:
memory to store reset signal information; and
a processor communicatively coupled to the memory, the processor configured to:
identify, from a synchronous circuit design, each of a plurality of synchronous state holding blocks that includes a reset signal associated with the reset signal information;
convert each of the plurality of synchronous state holding blocks to a corresponding asynchronous dataflow logic block that includes a reset input to generate an asynchronous circuit design that is equivalent to the synchronous circuit design; and
distribute to a location of the asynchronous dataflow logic block a replicated reset token, an operational frequency of the replicated reset token being a fraction of an operational frequency of the reset signal.
11. The system of claim 10 , wherein the processor is configured to:
identify each of the plurality of synchronous state holding blocks that includes an asynchronous reset signal.
12. The system of claim 11 , further comprising:
a converter to convert an operational frequency of the asynchronous reset signal to an operational frequency of a clock domain corresponding to the at least one of the plurality of synchronous state holding blocks.
13. The system of claim 10 , further comprising:
an upsampler to upsample the replicated reset token at the location of the asynchronous dataflow logic block and provide an upsampled reset token at the reset input of the asynchronous dataflow logic block.
14. The system of claim 13 , wherein the upsampler is to upsample the replicated reset token to an operational frequency substantially the same as the operational frequency of the reset signal.
15. The system of claim 10 , wherein the asynchronous dataflow logic block comprises:
at least one modified initial block that includes at least one of an upsampler or a local reset value register that stores a reset value corresponding to a current value of the replicated reset token.
16. The system of claim 10 , further comprising:
a display unit to display the asynchronous dataflow logic block.
17. An integrated circuit comprising:
a plurality of asynchronous logic circuits, at least one of the plurality of asynchronous logic circuits implementing an asynchronous dataflow logic block that corresponds to at least one of a synchronous state holding block of a synchronous circuit that is coupled to a reset signal, the asynchronous dataflow logic block having a reset input or a reset line that distributes a replicated reset token to a location of the asynchronous dataflow logic block, an operational frequency of the replicated reset token being a fraction of an operational frequency of the reset signal.
18. The integrated circuit of claim 17 , wherein the synchronous state holding block of the synchronous circuit is coupled to an asynchronous reset signal.
19. The integrated circuit of claim 18 , wherein at least one of the plurality of asynchronous logic circuits comprises:
a converter to convert an operational frequency of the asynchronous reset signal to an operational frequency of a clock domain including at least one of the synchronous state holding blocks.
20. The integrated circuit of claim 17 , wherein at least one of the plurality of asynchronous logic circuits implements the asynchronous dataflow logic block that corresponds to an upsampler that operates to upsample the replicated reset token to provide an upsampled reset token at the location of the asynchronous dataflow logic block.
21. The integrated circuit of claim 17 , wherein the upsampled reset token has an operational frequency substantially the same as the operational frequency of the reset signal.
22. The integrated circuit of claim 17 , wherein the asynchronous dataflow logic block comprises at least one modified initial block that includes at least one of an upsampler or a local reset value register that operates to store a reset value corresponding to a current value of the replicated reset token.
23. A machine-readable device storing instructions, which when executed by a machine cause the machine to perform operations comprising:
identifying, from a synchronous circuit design, each of a plurality of synchronous state holding blocks that includes a reset signal;
converting each of the plurality of synchronous state holding blocks to a corresponding asynchronous dataflow logic block that includes a reset input to generate an asynchronous circuit design that is equivalent to the synchronous circuit design; and
distributing to a location of the asynchronous dataflow logic block a replicated reset token, an operational frequency of the replicated reset token being a fraction of an operational frequency of the reset signal.
24. The machine-readable device of claim 23 , wherein the operations further comprise:
upsampling the replicated reset token at the location of the asynchronous dataflow logic block; and
providing, at the reset input of the asynchronous dataflow logic block, an upsampled reset token.