Device and method for providing a reference signal

1. A method for providing a sampled voltage to pixels of a pixel array, the method comprising:

sampling an input voltage during a sampling phase to provide a sampled voltage, wherein the sampling comprises:

providing the input voltage to a source of an transistor; providing a gate circuit, from a bootstrap circuit, to a gate of the transistor; wherein the gate voltage exceeds a supply voltage; and

allowing a capacitor that is coupled to a drain of the transistor to be charged to the input voltage to provide a sampled voltage;

storing, during a hold phase, the sampled voltage and outputting the sampled voltage to multiple pixels of a pixel array; wherein the storing comprises:

keeping the gate, source and drain of the transistor at the same potential; and

disconnecting the source of the transistor from an input port through which the input voltage was provided;

wherein the transistor is an NMOS transistor;

wherein the method further comprises:

grounding a bulk of the NMOS transistor during the sampling phase;

disconnecting the bulk of the NMOS transistor from the ground during the hold phase; and

disconnecting the gate of the NMOS transistor from the bootstrap circuit during the hold phase.

2. The method according to claim 1 comprising sampling the input during a sampling phase that does not exceed 5 microseconds.

3. The method according to claim 1 wherein the NMOS transistor has a high threshold voltage.

4. The method according to claim 1 wherein the sampling comprises:

providing, by a buffer, an input voltage to a first input of the bootstrap circuit;

providing to a second input of the bootstrap circuit a control signal that changes between phases of the sample period; and

receiving from the bootstrap circuit a gate voltage that substantially equals the supply voltage plus the input voltage.

5. A device, comprising a pixel array, an interfacing circuit and a sample and hold circuit;

wherein the interfacing circuit directs to at least one pixel of the pixel array a sampled voltage that is outputted from the sample and hold circuit;

wherein the sample and hold circuit comprises an transistor, a bootstrap circuit, a capacitor, sample phase switches and hold phase switches;

wherein during the sample phase the source of the transistor receives the input voltage; the gate of the transistor receives, from the bootstrap circuit a gate voltage that exceeds a supply voltage; and a capacitor of the sample and hold circuit is charged to the input voltage to provide the sampled voltage;

wherein during a hold phase the capacitor stores the sampled voltage; the gate, source and drain of the transistor are maintained at the same potential; and the source of the transistor is disconnected from an input port through which the input voltage was provided;

wherein the transistor is an NMOS transistor;

wherein a bulk of the NMOS transistor is grounded during the sampling phase; wherein the bulk of the NMOS transistor is disconnected from the ground during the hold phase; and wherein the gate of the NMOS transistor is disconnected from the bootstrap circuit during the hold phase.

6. The device according to claim 5 wherein the sample and hold circuit is configured to sample the input during a sampling phase that does not exceed 5 microseconds.

7. The device according to claim 5 wherein the NMOS transistor has a high threshold voltage.

8. The device according to claim 5 wherein the sample and hold circuit further comprises a buffer that is coupled between a first input of the bootstrap circuit and a source of the bootstrap circuit; wherein a second input of the bootstrap circuit receives a control signal that changes between phases of the sample period; and wherein the bootstrap circuit is configured to provide to the gate of the NMOS transistor a gate voltage that substantially equals the supply voltage plus the input voltage.