Co-packaging approach for power converters based on planar devices, structure and method
A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.
1. A method of forming a semiconductor voltage converter, comprising:
forming a high-side transistor comprising a lateral diffusion metal oxide semiconductor (LDMOS) device on a substrate of a semiconductor die, wherein forming the high-side transistor includes patterning a gate conductor layer to form a gate of the LDMOS device;
forming a low-side transistor comprising a vertical diffusion metal oxide semiconductor (VDMOS) device on the substrate of the semiconductor die such that the LDMOS device and the VDMOS device are electrically coupled to one another via the substrate, wherein forming the low-side transistor includes patterning said gate conductor layer to form a gate of the VDMOS device such that the gate of the LDMOS device and the gate of the VDMOS device are coplanar; and
forming a single conductive structure which forms:
a gate shield which is interposed between at least one conductive gate portion of the LDMOS device and a conductive structure which overlies the gate shield; and
a trench conductor electrically coupled to a semiconductor substrate and to a source region of the LDMOS device.
2. The method of claim 1 wherein the semiconductor die is a first semiconductor die, and the method further comprises:
forming a voltage converter controller circuit on a second semiconductor die different from the first semiconductor die; and
electrically coupling an output circuit on the first semiconductor die comprising the LDMOS device and the VDMOS device to the controller circuit on the second semiconductor die.
3. The method of claim 2 , further comprising co-packaging the first semiconductor die and the second semiconductor die into a single semiconductor device.
4. The method of claim 1 further comprising forming a second single conductive structure which forms:
a drain interconnect which electrically couples a drain of the LDMOS device to voltage in (V IN ); and
a source interconnect which electrically couples a source of the VDMOS device to ground.
5. The method of claim 1 , further comprising:
providing a semiconductor substrate having a back side;
forming an output stage of the semiconductor voltage converter using a method which comprises the formation of the high-side transistor and the low-side transistor; and
doping the semiconductor substrate to a dopant concentration of about 1E18 to 1E20 atoms/cm 3 such that, during operation of the semiconductor voltage converter, a back side of the semiconductor substrate is adapted to function as a switched node of the output stage.
6. The method of claim 1 , further comprising:
providing a semiconductor substrate comprising a semiconductor wafer;
forming an epitaxial layer having a thickness over the semiconductor wafer;
etching through the epitaxial layer to expose the semiconductor wafer and to form a trench within the epitaxial layer and within the semiconductor wafer; and
forming the trench conductor within the trench.
7. The method of claim 1 , wherein forming the high-side transistor and forming the low-side transistor further comprises forming the high-side transistor and forming the low-side transistor such that a source of the LDMOS is electrically coupled to a drain of the VDMOS via the substrate.