IP Library Granted Patent US 8,168,532
Granted Patent B2
US 8,168,532 · App. 12/267,970 · Granted May 1, 2012

Method of manufacturing a multilayer interconnection structure in a semiconductor device

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,168,532
App. No.
12/267,970
Granted
May 1, 2012
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.

Claims (29)

1. A method for manufacturing a semiconductor device, the method comprising:

forming a transistor having at least a gate electrode and a source and drain region on a semiconductor substrate;

forming an insulating film containing oxygen over the semiconductor substrate;

forming a concave portion in the insulating film;

forming a metal film containing Cu—Mn alloy on an inner wall and a bottom surface of the concave portion and on the insulating film;

etching the metal film to thin said metal film formed on the inner wall while removing the metal film formed on the insulating film and on the bottom surface of the concave portion;

forming a copper containing film over the metal film, the copper containing film filling the concave portion; and

conducting a heat treatment after formation of the film containing copper.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the Mn concentration in the metal film is 0.2 atomic percent to 30 atomic percent and the film thickness is within the range of 1 nm to 15 nm.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the Mn concentration in the metal film is 0.2 atomic percent to 100 atomic percent and the film thickness is 1 nm to 4.5 nm.

4. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming a seed film containing copper on the metal film.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the metal film is formed by a sputtering method.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the formation of the copper-containing film filling the concave portion comprises the steps of forming the copper-containing film filling the concave portion by an electroplating method and conducting a heat treatment at a temperature of 80° to 120° after formation of the copper-containing film by the electroplating method.

7. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming a diffusion preventing film for preventing a diffusion of copper between the insulating film and the metal film.

8. The method for manufacturing a semiconductor device according to claim 7 , wherein the diffusion preventing film is a high-melting point metal film containing at least one element selected from the group consisting of Ta, Ti, Zr, and Ru.

9. The method for manufacturing a semiconductor device according to claim 1 , wherein the Mn concentration in the metal film is 0.2 atomic percent to 30 atomic percent and the film thickness is less than or equal to 15 nm.

10. The method for manufacturing a semiconductor device according to claim 9 , comprising the step of conducting etching so as to achieve a predetermined film thickness after film formation of the metal film.

11. A method for manufacturing a semiconductor device, the method comprising:

forming a transistor having a gate electrode and a source and drain region on a semiconductor substrate;

forming an oxygen-containing insulating film over the semiconductor substrate;

forming a concave portion in the insulating film;

forming a metal film containing Cu—Mn alloy on an inner wall and a bottom surface of the concave portion and the insulating film;

etching the metal film to thin said metal film formed on the inner wall while removing the metal film formed on the insulating film and on the bottom surface of the concave portion;

forming a copper containing film over the metal film, the copper containing film filling the concave portion; and

conducting a heat treatment after formation of the copper-containing film,

wherein the film thickness of the metal film is specified to be 15 nm or less in the case where the Mn concentration x in terms of atomic percent in the metal film is within the range of 0 atomic percent<x<30 atomic percent, and

the film thickness is specified to be equal to or less than the film thickness y (nm), where y is given by a formula y=465 (atomic percent·nm)/x in the case where the Mn concentration x is within the range of 30 atomic percent ≦x≦100 atomic percent.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the formation of the copper-containing film filling the concave portion comprises the steps of forming the copper-containing film filling the concave portion by an electroplating method and conducting a heat treatment at a temperature of 80° C. to 120° C. after formation of the copper-containing film by the electroplating method.

13. The method for manufacturing a semiconductor device according to claim 11 , wherein the heat treatment is conducted for 60 to 250 seconds.

Assignments (3)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2008
From: HANEDA, MASAKI; SUNAYAMA, MICHIE; SHIMIZU, NORIYOSHI; OHTSUKA, NOBUYUKI; NAKAO, YOSHIYUKI; TABIRA, TAKAHIRO
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021850/0952 →
Priority Claims (2)
JP 2007-295778 · Nov 14, 2007 · national
JP 2008-163798 · Jun 23, 2008 · national
Continuity (1)
Related Publication 20090121355A1 · May 14, 2009