IP Library › Granted Patent US 8,171,170
Granted Patent B2
US 8,171,170 · App. 10/836,104 · Granted May 1, 2012

Storage switch task processing synchronization

Assignee: EMC Corporation
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Quick Facts
Patent No.
US 8,171,170
App. No.
10/836,104
Filed
Apr 30, 2004
Granted
May 1, 2012
Kind
B2
Art Unit
2451
USPC
709/248
Abstract

Systems and methods in accordance with various embodiments relate to a storage switch including task processing synchronization. In embodiments of the present invention, the packet processing units may generate and store Task Index and Generation Count information that prevents the processing of expired commands or responses. Additionally or alternatively, embodiments of the present invention may further employ timeout sequences to prevent previous instances of a stale task resource from disrupting the current use of the task resource.

Claims (64)

1. A method of maintaining task synchronization between first and second processors within a switch of a network, comprising the steps of:

(a) provisioning information upon receipt of a data unit at a first time to be routed through the first and second processors, the information uniquely identifying the data unit;

(b) provisioning a count uniquely identifying the data unit at said first time, the count capable of incrementing to identify other data units;

(c) associating said identifier and count with a response to a task generated at a second time; and

(d) using the information and a second count associated with said response to maintain a synchronized state between the first and second processors performing a processing task on said data unit.

2. A method of maintaining task synchronization between first and second processors as recited in claim 1 , wherein the information comprises an identifier and a count.

3. A method of maintaining task synchronization between first and second processors as recited in claim 1 , wherein the task relates to performing one of a read operation, a write operation or a verify operation.

4. A method of maintaining task synchronization between first and second processors as recited in claim 1 , further comprising the steps of:

(c) provisioning a timeout period within at least one of the first and second processors; and

(d) using the timeout period to maintain a synchronized state between the first and second processors.

5. A method of maintaining task synchronization between first and second processors as recited in claim 1 , wherein the data unit is in a Fiber Channel IU.

6. A method of maintaining task synchronization between first and second processors as recited in claim 1 , wherein the data unit is in an iSCSI PDU.

7. A method of maintaining task synchronization between first and second processors as recited in claim 1 , wherein said step (b) of using the information to maintain a synchronized state between the first and second processors comprises the steps of:

(c) storing the information in memory associated with the first processor;

(d) sending the data unit with the information from the first processor to the second processor, the first processor capable of altering the information stored in memory upon receipt of a new data unit thereafter;

(e) returning a response relating to the data unit from the second processor to the first processor, the response including returned information;

(f) comparing the returned information with the information stored in memory; and

(g) discarding the response if the returned information and stored information are different.

8. A method of maintaining task synchronization between processors within a switch of a network, comprising the steps of:

(a) generating and maintaining within said switch information uniquely representing a task upon receipt of the task at a time t 1 , the information capable of changing upon receipt of subsequent tasks;

(b) generating at said time t 1 a count further identifying said task, said count being capable of incrementing thereafter to identify other tasks;

(c) associating the information and the count generated at said time t 1 with other information and another count in a response to the task at a time t 2 after time t 1 ; and

(d) comparing the other information and other count in said response with the information and count generated at said time t 1 to maintain task synchronization.

9. A method of maintaining task synchronization within a switch of a network as recited in claim 8 , further comprising a step (d) of discarding the response generated in said step (b) if the other information generated in said step (b) is different than the information generated and maintained in said step (a).

10. A method of maintaining task synchronization within a switch of a network as recited in claim 8 , wherein the unique information comprises an identifier.

11. A method of maintaining task synchronization between first and second processors within a switch of a network, comprising the steps of:

(a) generating a first count upon receipt by the first processor of a task from an initiator at a time t 1 , the first count uniquely identifying the task and being capable of incrementing thereafter for another task;

(b) generating a first identifier at time t 1 further identifying the task; and

(c) comparing the first count and the first identifier with a second count and a second identifier associated with a response generated by a target in response to the task at a time t 2 after the time t 1 to maintain task synchronization before processing the response by the second processor.

12. A method of maintaining task synchronization between first and second processors as recited in claim 11 , the task comprising one of performing a read operation, a write operation or a verify operation.

13. A method of maintaining task synchronization between first and second processors as recited in claim 11 , wherein the task is communicated in one of iSCSI or Fibre Channel protocols.

14. A method of maintaining task synchronization between first and second processors as recited in claim 11 , wherein the first processor is in communication with an initiator.

15. A method of maintaining task synchronization between first and second processors as recited in claim 14 , wherein the initiator is a server.

16. A method of maintaining task synchronization between first and second processors as recited in claim 11 , wherein the second processor is in communication with a target.

17. A method of maintaining task synchronization between first and second processors as recited in claim 16 , wherein the target is one or more physical storage devices.

18. A method of maintaining task synchronization between first and second processors as recited in claim 11 , wherein the task relates to the processing of a data unit routed between the first and second processors through the fabric of the switch.

19. A method of maintaining task synchronization between first and second processors within a switch of a network, the first and second processors capable of routing a data unit between an initiator of the data unit and a target for the data unit, the method comprising the steps of:

(a) provisioning an identifier identifying the data unit at a time t 1 ;

(b) provisioning a count further identifying the data unit at the time t 1 , the count capable of incrementing thereafter to identify other data units, said identifier and count uniquely identifying the data unit;

(c) storing the identifier and count provisioned at time t 1 in said steps (a) and (b);

(d) associating the identifier and the count provisioned at time t 1 in said steps (a) and (b) with a response generated within the second processor in response to the task at time t 2 after the time t 1 ; and

(e) comparing another count associated with the response in said step (d) with the count stored in said step (c) to maintain task synchronization.

20. A method of maintaining task synchronization between first and second processors as recited in claim 19 , the task comprising one of performing a read operation, a write operation or a verify operation.

21. A method of maintaining task synchronization between first and second processors as recited in claim 19 , wherein the task is communicated in one of iSCSI or Fibre Channel protocols.

22. A method of maintaining task synchronization between first and second processors as recited in claim 19 , further comprising the step of discarding the response generated in said step (d) if the other count associated with the response in said step (d) is not the same as the count stored in said step (c).

23. A method of maintaining task synchronization between first and second processors as recited in claim 19 , further comprising the step of releasing any resources allocated for the response generated in said step (d) if the other count associated with the response in said step (d) is not the same as the count stored in said step (c).

24. A method of maintaining task synchronization between first and second processors as recited in claim 19 , further comprising the step of informing the initiator of the result if the other count associated with the response in said step (d) is not the same as the count stored in said step (c).

25. A system of maintaining task synchronization between first and second processors within a switch of a network, the system comprising:

means for provisioning information upon receipt of a data unit at a first time to be routed through the first and second processors, the information uniquely identifying the data unit;

means for provisioning a count further identifying the data unit at said first time, the count capable of incrementing thereafter to identify other data units;

means for associating said identifier and said count with a response to a task generated within the second processor at a second time; and

means for using the information and the count associated with said response to maintain a synchronized state between the first and second processors.

26. A system of maintaining task synchronization between first and second processors as recited in claim 25 , wherein the information comprises an identifier.

27. A system of maintaining task synchronization between first and second processors as recited in claim 25 , wherein the data unit relates to performing a read operation, a write operation or a verify operation.

28. A system of maintaining task synchronization between first and second processors as recited in claim 25 , further comprising:

means for provisioning a timeout period within at least one of the first and second processors; and

means for using the timeout period to maintain a synchronized state between the first and second processors.

29. A system of maintaining task synchronization between first and second processors as recited in claim 25 , wherein the data unit is in a Fiber Channel IU.

30. A system of maintaining task synchronization between first and second processors as recited in claim 25 , wherein the data unit is in an iSCSI PDU.

31. A system of maintaining task synchronization between first and second processors as recited in claim 25 , said means of using the information to maintain a synchronized state between the first and second processors comprising:

a memory associated with the first processor for storing the information;

the first processor sending the data unit with the information to the second processor, the first processor capable of altering the stored information upon receipt of a new data unit thereafter;

the first processor comparing returned information in a response by the second processor to the data unit with the information stored in said memory and

discarding the response if the returned information and stored information are different.

Assignments (11)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 040203/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2005
From: MARANTI NETWORKS, INC.
To: EMC CORPORATION
Reel/Frame 016327/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2004
From: FREY, ROBERT TOWER; ZHANG, CHAO
To: MARANTI NETWORKS, INC.
Reel/Frame 015643/0264 →
Continuity (1)
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