Integrated circuit structures with multiple FinFETs
View Patent ↗A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.
1. A device comprising:
a semiconductor substrate;
Shallow Trench Isolation (STI) regions at a surface of the semiconductor substrate, wherein the STI regions comprise a flat top surface;
a semiconductor strip between opposite sidewalls of the STI regions, wherein a portion of the semiconductor strip over the flat top surface of the STI regions forms a semiconductor fin, wherein the semiconductor fin forms a channel region of a Fin field-effect transistor (FinFET), and wherein the semiconductor strip is connected to the semiconductor substrate to form a continuous semiconductor region;
a gate dielectric on sidewalls and a top surface of the semiconductor fin;
a gate electrode on the gate dielectric;
a source/drain region of the FinFET connected to an end of the semiconductor fin, wherein the source/drain region has a source/drain junction; and
a source/drain silicide region on sidewalls and a top surface of the source/drain region, wherein the source/drain junction is higher than the flat top surface of the STI regions
a spacer vertically between the source/drain silicide region and the flat top surface of the STI region, wherein the spacer comprises an inner edge adjoining the semiconductor fin, and a curved outer edge opposite the inner edge.
2. The device of claim 1 , wherein one of the STI regions underlying and in contact with the spacer extends from a portion substantially aligned to the inner edge of the spacer to a portion beyond the outer edge of the spacer.
3. The device of claim 1 , wherein the spacer comprises:
a top end adjoining a bottom end of the source/drain silicide region; and
a bottom end adjoining the flat top surface of the STI regions.