Compact low loss high frequency switch with improved linearity performance
A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.
1. A switch element, comprising:
a switch device having a drain, a source and a plurality of gates located between the drain and the source; and
at least one additional interconnect located among the plurality of gates, the additional interconnect implemented to establish a substantially constant potential between the plurality of gates.
2. The switch element of claim 1 wherein the switch element includes at least three gates and at least two additional interconnects interleaved with the at least three gates.
3. The switch element of claim 1 wherein the plurality of gates are configured as ohmic contacts.
4. The switch element of claim 1 wherein the plurality of gates are configured as Schottky contacts.
5. The switch element of claim 1 wherein a pair of switch devices are coupled together.
6. The switch element of claim 1 wherein the at least one additional interconnect has a line width of approximately 0.5 μm.
7. The switch element of claim 1 wherein the at least one additional interconnect has a line width of approximately 0.5 μm and each of the plurality of gates has a line width of approximately 0.5 μm.
8. A portable transceiver, comprising:
an antenna;
a transmitter and a receiver, each operatively coupled to the antenna; and
switch element operatively coupled to the transmitter and to the receiver, the switch element including a switch device having a drain, a source and a plurality of gates located between the drain and the source; and at least one additional interconnect located among the plurality of gates, the additional interconnect implemented to establish a substantially constant potential between the plurality of gates.
9. The transceiver of claim 8 wherein the switch element includes at least three gates and at least two additional interconnects interleaved with the at least three gates.
10. The transceiver of claim 8 wherein the plurality of gates are configured as ohmic contacts.
11. The transceiver of claim 8 wherein the plurality of gates are configured as Schottky contacts.
12. The transceiver of claim 8 wherein a pair of switch devices are coupled together.
13. The transceiver of claim 8 wherein the at least one additional interconnect has a line width of approximately 0.5 μm.
14. The transceiver of claim 8 wherein the at least one additional interconnect has a line width of approximately 0.5 μm and in which each of the plurality of gates has a line width of approximately 0.5 μm.
15. A switch element, comprising:
a source;
a drain;
a plurality of gates disposed between the source and the drain; and
at least one interconnect disposed adjacent to at least one of the gates so as to reduce or substantially eliminate a floating node effect on the gates.
16. The switch element of claim 15 wherein each of the gates and the at least one interconnect is implemented as a trace.
17. The switch element of claim 16 wherein the gate traces and the at least one interconnect trace extend in a substantially parallel manner.
18. The switch element of claim 15 wherein the at least one interconnect is connected to resistance Rlin between the source and the drain.
19. The switch element of claim 15 wherein the switch element includes N gates and N−1 interconnects arranged in an interleaved manner.
20. The switch element of claim 15 wherein the gates and the at least one interconnect are implemented as ohmic contacts.
21. The switch element of claim 15 wherein the gates and the at least one interconnect are implemented as Schottky contacts.
22. The switch element of claim 15 wherein the gates are grouped into two or more groups such that the at least one interconnect is located between two neighboring groups.
23. A switch element, comprising:
a source;
a drain;
a plurality of gate structures disposed between the source and the drain, at least one of the gate structures connected to resistance Rlin between the source and the drain so as to reduce or substantially eliminate a floating node effect on the gate structures.