Controlling access to an embedded memory of a microcontroller
A microcontroller ( 30 ) includes a processor ( 32 ), an embedded memory ( 46 ) operatively coupled to the processor ( 32 ), and a microcontroller test interface ( 34 ) operatively connected to the processor ( 32 ) and the memory ( 36 ). The microcontroller ( 30 ) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface ( 34 ) to be set and execution of initiation code with the processor ( 32 ). This code execution optionally establishes a further disabled state. The microcontroller ( 30 ) provides an enabled state of the test interface for memory ( 46 ) access through the test interlace ( 34 ) during microcontroller ( 30 ) operation subsequent to the reset initiation unless the further disabled memory ( 46 ) access state is established by execution of the initiation code.
1. A method, comprising:
establishing reset initiation operation of a microcontroller, the microcontroller including an embedded memory, programmable processor, and a test interface operatively coupled to the memory and the processor;
during the reset initiation operation of the microcontroller, establishing a first disabled state of the test interface to disable access to the memory through the test interface;
executing reset programming stored in the memory with the processor to optionally establish a second disabled state of the test interface during the first disabled state; and
enabling memory access through the test interface for microcontroller operation after the reset initiation operation unless the second disabled state is established by execution of the reset programming, the second disabled state disabling the memory access through the test interface during the microcontroller operation after the reset initiation operation.
2. The method of claim 1 , wherein the first disabled state is established by the reset programming.
3. The method of claim 1 , which includes inhibiting the enabling of the memory access in response to optional establishment of the second disabled state through the execution of the reset programming.
4. The method of claim 3 , which includes altering contents of the memory during the microcontroller operation after the reset initiation operation to gain memory access through the test interface.
5. The method of claim 4 , wherein the altering includes at least one of erasing the memory and storing different contents in the memory through an external memory port.
6. The method of claim 1 , wherein the establishing of the first disabled state is performed in accordance with operating logic in response to a reset signal.
7. The method of claim 1 , wherein the test interlace is operable to perform JTAG operations when enabled.
8. A method, comprising:
resetting a microcontroller including an embedded memory, a programmable processor, and a test interface operatively coupled to the memory and the processor;
in response to the resetting, executing reset initiation code stored in the memory with the processor, the initiation code disabling access to the memory through the test interface to protect memory contents during microcontroller operation subsequent to the resetting; and
during the microcontroller operation subsequent to the resetting, changing the contents of the memory to enable access to the memory through the test interface.
9. The method of claim 8 , wherein the disabling access includes establishing an initial disabled stated of the test interface and a further disabled state of the test interlace with the initiation code, the initial disabled state denying access during reset processing and the further disabled state inhibiting enabling of memory access through the test interface during the microcontroller operation subsequent to the resetting to prevent the contents of the memory from being read through the test interface.
10. The method of claim 8 , wherein the changing of the contents of the memory during the microcontroller operation subsequent to the resetting includes erasing at least a portion of the contents of the memory to gain memory access through the test interlace.
11. The method of claim 8 , wherein the changing of the contents of the memory during the microcontroller operation subsequent to the resetting includes storing different contents in at least a portion of the memory to gain memory access through the test interface.
12. The method of claim 8 , wherein:
the changing includes at least one of: erasing the memory and storing different contents in the memory; and
the reset initiation code is stored in a predefined portion of the memory and the memory is nonvolatile.
13. The method of claim 8 , which includes providing a first disabled state of the test interface in response to the resetting before completing execution of the reset initiation code and establishing a second disabled state of the test interface through the execution of the reset initiation code.
14. The method of claim 8 , wherein the first disabled state is set in response to operating logic of the microcontroller.
15. Apparatus, comprising: a microcontroller integrated circuit including a processor, an embedded memory, and a microcontroller test interface operatively connected to the processor and the memory, the microcontroller being responsive to a reset signal to perform a reset initiation, the reset initiation being operable to set an initial disabled state to memory access through the test interface and execute initiation code with the processor during the initial disabled state to optionally establish a further disabled state for the memory access through the test interface, the microcontroller providing an enabled state for access to the memory through the test interface during microcontroller operation subsequent to the reset initiation unless the further disabled state is established by execution of the initiation code.
16. The apparatus of claim 15 , wherein the microcontroller includes means for performing input and output operations through the test interface with external equipment in accordance with a JTAG protocol.
17. The apparatus of claim 15 , wherein the microcontroller is responsive to one or more signals to alter contents of the memory after the further disabled state is set to change contents of the memory and enable memory access through the test interlace.
18. The apparatus of claim 15 , wherein the microcontroller includes means for changing contents of the memory after the further disabled state is set by the execution of the initiation code.
19. The apparatus of claim 15 , wherein the memory is of a nonvolatile flash type and the initiation code is stored in the memory relative to at least one reserved memory location.
20. The apparatus of claim 15 , wherein the initiation code is executable to set the initial disabled state of the test interface.
21. The apparatus of claim 15 , wherein the microcontroller is structured to set the initial disabled state in response to the reset initiation before execution of the initiation code commences.
22. A method, comprising:
resetting a microcontroller including an embedded memory, a programmable processor, and a test interface operatively coupled to the memory and the processor;
in response to the resetting, executing initiation code stored in the memory;
during the executing, establishing an initial disabled state of the test interface to protect contents of the memory from access through the test interface and optionally establishing a further disabled state of the test interface; and
after the executing, establishing an enabled state of the test interface that enables access to the contents of the memory through the test interface during subsequent microcontroller operation unless the further disabled state is established by execution of the initiation code.
23. The method of claim 22 , which includes inhibiting the enabling of the memory access in response to optional establishment of the further disabled state through the execution of the reset programming.
24. The method of claim 23 , which includes altering contents of the memory during the microcontroller operation after the resetting to gain memory access through the test interface.
25. The method of claim 24 , wherein the altering includes at least one of erasing the memory and storing different contents in the memory through an external memory port.
26. The method of claim 24 , wherein the test interface is operable to perform JTAG operations when enabled, the memory is of a nonvolatile type, and the initiation code is stored in the memory relative to one or more predefined memory locations.