Flash memory devices including ready/busy control circuits and methods of testing the same
A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in response to the chip disable signal and externally outputs the ready/busy signal through a ready/busy output pin.
1. A flash memory device, comprising:
a ready/busy output pin that outputs a ready/busy signal representing an internal operational state of the flash memory device;
a chip disable fuse circuit that includes a fuse and that outputs a chip disable signal when the fuse is cut out; and
a ready/busy control circuit that activates the ready/busy signal output through the ready/busy output pin in response to the chip disable signal.
2. The flash memory device of claim 1 , further comprising:
a command receipt circuit that receives external commands;
a flash memory internal circuit that operates in response to the commands input through the command receipt circuit; and
a short current generation circuit that allows a short current to flow in response to the chip disable signal.
3. The flash memory device of claim 2 , wherein the ready/busy signal is set to a first logic level when the flash memory internal circuit performs data programming, deletion, and/or reading operations, and the ready/busy signal is set to a second logic level, different from the first logic level, when the flash memory internal circuit completes the data programming, deletion, and/or reading operations.
4. The flash memory device of claim 2 , wherein the command receipt circuit is configured to process the commands input thereto regardless of the state of the ready/busy signal.
5. The flash memory device of claim 2 , wherein the command receipt circuit processes the commands in response to a chip enable signal input through a chip enable pin.
6. The flash memory device of claim 2 , further comprising a ready/busy signal output circuit including a pull-up resistor and a pull-down transistor connected in series between a power voltage and a ground voltage, the ready/busy output pin being connected between the pull-up resistor and the pull-down transistor,
wherein the ready/busy control circuit comprises:
a first inverter that inverts the chip disable signal;
a NAND gate that receives an output signal from the inverter and an internal ready/busy signal generated in the flash memory internal circuit; and
a second inverter that inverts an output signal of the NAND gate to generate a ready/busy control signal and provides the ready/busy control signal to a gate of the pull-down transistor.
7. The flash memory device of claim 2 , wherein the chip disable fuse circuit comprises:
a P-MOS transistor having a source to which a power voltage is applied, a gate to which a control signal is applied, and a drain to which an output node for outputting the chip disable signal is connected; and
a fuse having one connected to the output node and another end connected to a ground voltage.
8. The flash memory device of claim 2 , wherein the short current generation circuit comprises:
an inverter that inverts the chip disable signal;
a P-MOS transistor having a source to which a power voltage is applied and a gate to which an output signal of the inverter is applied; and
an N-MOS transistor having a drain to which a drain of the P-MOS transistor is connected, a gate to which the chip disable signal is applied, and a source to which a ground voltage is applied.
9. A method of testing a flash memory device, comprising:
activating a chip disable signal by cutting out a fuse for disabling a chip in the flash memory device;
activating a ready/busy signal representing an operational state of the flash memory device in response to activating the chip disable signal;
outputting the activated ready/busy signal outside of the flash memory device through the ready/busy output pin; and
determining, in response to the ready/busy signal, that the flash memory device is not operational.
10. The method of claim 9 , further comprising flowing an electrical short current in response to activating the chip disable signal.
11. The method of claim 9 , wherein the ready/busy signal is set to a first logic level when the flash memory device performs data programming, deletion, and/or reading operations, and the ready/busy signal is set to a second logic level, different from the first logic level, when the flash memory device completes the data programming, deletion, and/or reading operations.
12. A flash memory device, comprising:
a flash memory core including a flash memory internal circuit;
an external output pin coupled to the flash memory core;
a chip disable fuse circuit that includes a fuse and that is configured to output a chip disable signal when the fuse is cut out; and
a control circuit that is configured to generate a control signal in response to the chip disable signal and to apply the control signal to the external output pin.
13. The flash memory device of claim 12 , further comprising:
a chip enable pin that is coupled to the flash memory core and that is configured to receive a chip enable signal; and
a command receipt circuit in the flash memory core that is configured to receive and process external commands in response to the chip enable signal irrespective of a state of the chip disable signal.
14. The flash memory device of claim 12 , wherein the external output pin comprises a ready/busy output pin that is configured to output a ready/busy signal indicative of an internal operational state of the flash memory device.
15. The flash memory device of claim 14 , further comprising:
a ready/busy control circuit that is configured, in response to the chip disable signal, to force the ready/busy signal to a logic level indicating that the flash memory device is not operational.
16. The flash memory device of claim 15 , wherein the logic level comprises a first logic level, and wherein the ready/busy signal is set to the first logic level when the flash memory internal circuit performs data programming, deletion, and/or reading operations, and the ready/busy signal is set to a second logic level, different from the first logic level, when the flash memory internal circuit completes the data programming, deletion, and/or reading operations.
17. The flash memory device of claim 15 , further comprising
a ready/busy signal output circuit including a pull-up resistor and a pull-down transistor connected in series between a power voltage and a ground voltage, the ready/busy output pin being connected between the pull-up resistor and the pull-down transistor,
wherein the ready/busy control circuit comprises:
a first inverter that inverts the chip disable signal;
a NAND gate that receives an output signal from the inverter and an internal ready/busy signal generated in the flash memory internal circuit; and
a second inverter that inverts an output signal of the NAND gate to generate a ready/busy control signal and provides the ready/busy control signal to a gate of the pull-down transistor.
18. The flash memory device of claim 13 , further comprising:
a flash memory internal circuit that operates in response to the commands input through the command receipt circuit; and
a short current generation circuit that allows a short current to flow in response to the chip disable signal.
19. The flash memory device of claim 12 , wherein the chip disable fuse circuit comprises:
a P-MOS transistor having a source to which a power voltage is applied, a gate to which a control signal is applied, and a drain to which an output node for outputting the chip disable signal is connected; and
a fuse having one connected to the output node and another end connected to a ground voltage.