Method for dual-channel nanowire FET device
View Patent ↗An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor includes a first group of nanowires made of silicon. The nanowire FET device may also include a second transistor on the same substrate, where the second transistor includes a second group of nanowires made of silicon-germanium.
1. A method of fabricating a nanowire FET (metal oxide semiconductor field effect transistor) device, the method comprising:
depositing, in at least two alternating layers, a first semiconductor material and a second semiconductor material to form a semiconductor structure;
etching a first layered column and a second layered column in the semiconductor structure;
forming a first group of nanowires, where the first group of nanowires comprises the first semiconductor material from the first layered column, and where a channel region in the first group of nanowires consists of the first semiconductor material;
forming a second group of nanowires, where the second group of nanowires comprises the second semiconductor material from the second layered column, and where a channel region in the second group of nanowires consists of the second semiconductor material and the second semiconductor material is different than the first semiconductor material;
depositing a first gate coupled to the first group of nanowires; and
depositing a second gate coupled to the second group of nanowires.
2. The method of claim 1 , where etching the first and second layered columns comprises:
depositing a first mask layer on the semiconductor structure, where the first mask layer comprises a pattern for the first and second layered columns; and
etching the semiconductor structure that is not masked by the first mask layer.
3. The method of claim 1 , where forming the first group of nanowires comprises:
forming a second mask layer on the second layered column;
etching the second semiconductor material from the first layered column; and
removing the second mask layer.
4. The method of claim 1 , where forming the second group of nanowires comprises:
forming a third mask layer on the first group of nanowires;
etching the first semiconductor material from the second layered column; and
removing the third mask layer.
5. The method of claim 1 , where the first semiconductor material is silicon (Si) and the second material is silicon-germanium (Si—Ge).
6. The method of claim 1 , where the first semiconductor material is a III-V material and the second semiconductor material is germanium (Ge).
7. The method of claim 1 , further comprising etching an insulator below the first layered column.
8. The method of claim 7 , further comprising etching the insulator below the second layered column.
9. The method of claim 1 , further comprising rounding the first group of nanowires.
10. The method of claim 9 , where rounding the first group of nanowires is accomplished using a hydrogen bake.
11. The method of claim 9 , where rounding the first group of nanowires is accomplished using oxidation.
12. The method of claim 1 , further comprising rounding the second group of nanowires.
13. The method of claim 12 , where rounding the second group of nanowires is accomplished using a hydrogen bake.
14. The method of claim 12 , where rounding the second group of nanowires is accomplished using oxidation.
15. The method of claim 1 , where forming a second group of nanowires comprises forming a third semiconductor layer coupled to the second semiconductor material.