Clock generation for memory access without a local oscillator
A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator.
1. An integrated circuit comprising:
(a) a first circuit for supporting a first circuit function;
(b) a second circuit for supporting a second circuit function;
(c) a digital interface circuit for receiving an oscillator signal from external to the integrated circuit;
(d) an oscillator circuit internal to the integrated circuit for providing a first clock signal; and
(e) a control circuit for in a first mode of operation enabling the first circuit and providing at least one of the first and second circuits with the first clock signal and in a second mode of operation for disabling the oscillator circuit internal to the integrated circuit, for disabling the second circuit, and for receiving the oscillator signal from external to the integrated circuit and driving the first circuit with the received oscillator signal,
wherein the first circuit comprises a serial presence detect circuit configured to perform a serial presence detect operation.
2. An integrated circuit according to claim 1 wherein, the first circuit comprises a memory circuit; and driving the first circuit comprises operating the memory circuit.
3. An integrated circuit according to claim 1 wherein, the digital interface circuit supports communications according to a digital communications protocol, the digital communications protocol being at least one of Inter-Integrated Circuit, Universal Serial Bus, System Management Bus, PMCIA, physical Ethernet, wireless Ethernet, PCI, SCI, SCSI, IEEE 488, RS-232, RS-422, RS-423, and SPI.
4. An integrated circuit according to claim 1 wherein, the digital interface circuit is an Inter-Integrated Circuit.
5. An integrated circuit according to claim 1 wherein, the first circuit comprises at least a phase locked loop, the phase locked loop synchronized in dependence upon at least the received oscillator signal.
6. An integrated circuit according to claim 5 wherein, the digital interface circuit supports communications according to a digital communications protocol, the digital communications protocol being at least one of Inter-Integrated Circuit, Universal Serial Bus, System Management Bus, PMCIA, physical Ethernet, wireless Ethernet, PCI, SCI, SCSI, IEEE 488, RS-232, RS-422, RS-423, and SPI.
7. An integrated circuit according to claim 5 wherein, the digital interface circuit is an Inter-Integrated Circuit.
8. An integrated circuit according to claim 2 wherein, the memory circuit is at least one of random access memory, read only memory and flash memory.
9. An integrated circuit according to claim 1 wherein, at least one of the first circuit, second circuit, digital interface circuit, oscillator circuit and control circuit is an integrated circuit, the integrated circuit being manufactured using a semiconductor technology based upon at least one of silicon, silicon-germanium, gallium arsenide, indium phosphide, gallium nitride and polymers.
10. A method comprising:
(a) providing a first circuit, the first circuit for supporting a first circuit function;
(b) providing a second circuit, the second circuit for supporting a second circuit function;
(c) providing a digital interface circuit, the digital interface circuit for receiving an oscillator signal from external to the integrated circuit; (d) providing an oscillator circuit, the oscillator circuit internal to the integrated circuit and for providing a first clock signal; and
(e) providing a control circuit, the control circuit for establishing a first mode of operation, the first mode of operation comprising at least enabling the first circuit and providing at least one of the first and second circuits with the first clock signal, and a second mode of operation, the second mode of operation comprising at least disabling the oscillator circuit internal to the integrated circuit, disabling the second circuit, and receiving the oscillator signal from external to the integrated circuit and driving the first circuit with the received oscillator signal,
wherein driving the first circuit comprises providing a serial presence detect operation.
11. A method according to claim 10 wherein, providing the first circuit comprises providing a memory circuit; and driving the first circuit comprises operating the memory circuit.
12. A method according to claim 10 wherein, providing the digital interface circuit comprises providing an interface supporting a digital communications protocol, the digital communications protocol being at least one of Inter-Integrated Circuit, Universal Serial Bus, System Management Bus, PMCIA, physical Ethernet, wireless Ethernet, PCI, SCI, SCSI, IEEE 488, RS-232, RS-4227, RS-423, and SPI.
13. A method according to claim 10 wherein, providing the digital interface circuit comprises providing an Inter-Integrated Circuit.
14. A method according to claim 10 wherein, driving the first circuit comprises providing at least a phase locked loop and synchronizing the phase locked loop in dependence upon at least the received oscillator signal.
15. A method according to claim 14 wherein, providing the digital interface circuit comprises providing an interface supporting a digital communications protocol, the digital communications protocol being at least one of Inter-Integrated Circuit, Universal Serial Bus, System Management Bus, PMCIA, physical Ethernet, wireless Ethernet, PCI, SCI, SCSI, IEEE 488, RS-232, RS-422, RS-423, and SPI.
16. A method according to claim 14 wherein, providing the digital interface circuit comprises providing an Inter-Integrated Circuit.
17. A method according to claim 11 wherein, providing the memory circuit comprises providing at least one of random access memory, read only memory and flash memory.
18. A method according to claim 10 wherein, providing at least one of the first circuit, second circuit, digital interface circuit, oscillator circuit and control circuit comprises providing an integrated circuit, the integrated circuit being manufactured using a semiconductor technology based upon at least one of silicon, silicon-germanium, gallium arsenide, indium phosphide, gallium nitride and polymers.
19. A computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device an integrated circuit is provided, comprising:
(a) a first circuit for supporting a first circuit function;
(b) a second circuit for supporting a second circuit function;
(c) a digital interface circuit for receiving an oscillator signal from external to the integrated circuit;
(d) an oscillator circuit internal to the integrated circuit for providing a first clock signal; and
(e) a control circuit for in a first mode of operation enabling the first circuit and providing at least one of the first and second circuits with the first clock signal and in a second mode of operation for disabling the oscillator circuit internal to the integrated circuit, for disabling the second circuit, and for receiving the oscillator signal from external to the integrated circuit and driving the first circuit with the received oscillator signal,
wherein the first circuit comprises a serial presence detect circuit configured to perform a serial presence detect operation.
20. A computer readable medium according to claim 19 wherein; the design of the integrated circuit comprises a memory circuit.
21. A computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device an integrated circuit is provided, comprising:
(a) a first circuit for supporting a first circuit function;
(b) a second circuit for supporting a second circuit function;
(c) an Inter-Integrated Circuit interface circuit for receiving a data clock signal from external to the integrated circuit;
(d) an oscillator circuit internal to the integrated circuit for providing a first clock signal; and
(e) a control circuit for in a first mode of operation enabling the first circuit and providing at least one of the first and second circuits with the first clock signal and in a second mode of operation for disabling the oscillator circuit internal to the integrated circuit, for disabling the second circuit, and for receiving the oscillator signal from external to the integrated circuit and driving the first circuit with the received data clock signal,
wherein driving the first circuit comprises providing a serial presence detect operation.
22. The integrated circuit of claim 2 , wherein the serial presence detect circuit is further configured to provide information with respect to a size, a data width, a speed and a voltage of the memory circuit of the first circuit.
23. The method of claim 11 , wherein the serial presence detect operation provides information with respect to a size, a data width, a speed and a voltage of the memory circuit of the first circuit.