IP Library Granted Patent US 8,188,471
Granted Patent B2
US 8,188,471 · App. 12/671,052 · Granted May 29, 2012

Field effect transistor

Assignee: Canon Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,188,471
App. No.
12/671,052
Granted
May 29, 2012
Kind
B2
Abstract

A field effect transistor is provided including a gate electrode (for example, 15 ), a source electrode ( 13 ), a drain electrode ( 14 ) and a channel layer ( 11 ) to control current flowing between the source electrode ( 13 ) and the drain electrode ( 14 ) by applying a voltage to the gate electrode ( 15 ). The channel layer ( 11 ) is constituted of an amorphous oxide containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40.

Claims (25)

1. A field effect transistor comprising:

a gate electrode;

a source electrode;

a drain electrode; and

a channel layer comprising an oxide material containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40.

2. The field effect transistor according to claim 1 , wherein the compositional ratio expressed by Si/(In+Si) is not less than 0.15 and not more than 0.30.

3. The field effect transistor according to claim 1 , wherein the compositional ratio expressed by Si/(In+Si) is not less than 0.15 and not more than 0.23.

4. A field effect transistor comprising:

a gate electrode;

a source electrode;

a drain electrode; and

a channel layer comprising an oxide material containing In, Zn and Si and having a compositional ratio of Si expressed by Si/(In+Zn+Si) of not less than 0.05 and not more than 0.40.

5. A field effect transistor comprising:

a gate electrode;

a source electrode;

a drain electrode;

a channel layer; and

a gate insulating layer in contact with said channel layer,

wherein said channel layer comprises an oxide material containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40, and

wherein said gate insulating layer comprises of an oxide or nitride, containing Si.

6. The field effect transistor according to claim 5 , wherein said gate insulating layer comprises a silicon oxide.

7. The field effect transistor according to claim 6 , wherein said channel layer and the gate insulating layer are formed by a sputtering method.

8. The field effect transistor according to claim 1 , wherein said oxide material is an amorphous oxide material.

9. The field effect transistor according to claim 4 , wherein said the oxide material is an amorphous oxide material.

10. The field effect transistor according to claim 5 , wherein said oxide material is an amorphous oxide material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2010
From: IWASAKI, TATSUYA; ITAGAKI, NAHO
To: CANON KABUSHIKI KAISHA
Reel/Frame 023987/0638 →
Priority Claims (2)
JP 2007-230381 · Sep 5, 2007 · national
JP 2008-146890 · Jun 4, 2008 · national
Continuity (1)
Related Publication 20100258794A1 · Oct 14, 2010