IP Library › Granted Patent US 8,188,484
Granted Patent B2
US 8,188,484 · App. 12/654,621 · Granted May 29, 2012

Semiconductor device

Assignee: Rohm Co., Ltd.
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Quick Facts
Patent No.
US 8,188,484
App. No.
12/654,621
Granted
May 29, 2012
Kind
B2
Abstract

The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.

Claims (24)

1. A semiconductor device comprising:

a semiconductor layer made of SiC and having a surface;

an impurity region formed on a surface layer portion of the semiconductor layer by doping the semiconductor layer with an impurity, the impurity forming a part of the surface of the semiconductor layer; and

a contact wire formed on the surface of the semiconductor layer in contact with the impurity region, wherein

the contact wire has at least a polysilicon layer and a metal layer, and has a multilayer structure obtained by successively laminating the polysilicon layer and the metal layer such that the polysilicon layer is in contact with the impurity region.

2. The semiconductor device according to claim 1 , further comprising:

a gate trench dug down from the surface of the semiconductor layer;

a first conductivity type body region formed in the semiconductor layer on a side portion of the gate trench;

a gate insulating film formed on the inner surface of the gate trench; and

a gate electrode embedded in the gate trench through the gate insulating film, wherein

the impurity region is a second conductivity type source region formed on a surface layer portion of the body region adjacently to the gate trench, and

the contact wire is a source wire in contact with the source region.

3. The semiconductor device according to claim 1 , further comprising:

a first conductivity type body region formed on a surface layer portion of the semiconductor layer;

a gate insulating film formed on the surface of the semiconductor layer; and

a gate electrode formed on the gate insulating film and opposed to the body region through the gate insulating film, wherein

the impurity region is a second conductivity type source region formed on a surface layer portion of the body region, and

the contact wire is a source wire in contact with the source region.

4. The semiconductor device according to claim 1 , wherein the polysilicon layer is a high-concentration doped layer doped with an impurity in a concentration of 10 19 to 10 21 cm −3 .

5. The semiconductor device according to claim 1 , wherein a layer containing titanium is interposed between the polysilicon layer and the metal layer.

6. The semiconductor device according to claim 5 , wherein

the metal layer has a layer containing Al, and

the layer containing titanium has a structure obtained by laminating a Ti layer and a TiN layer in this order from the side closer to the polysilicon layer.

7. The semiconductor device according to claim 1 , wherein the polysilicon layer is doped with at least one type of conductive impurity selected from a group consisting of B, P, Al and N.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2010
From: NAKANO, YUKI
To: ROHM CO., LTD.
Reel/Frame 024230/0316 →
Priority Claims (3)
JP 2008-330317 · Dec 25, 2008 · national
JP 2008-334480 · Dec 26, 2008 · national
JP 2009-293361 · Dec 24, 2009 · national
Continuity (1)
Related Publication 20100193796A1 · Aug 5, 2010