IP Library Granted Patent US 8,188,540
Granted Patent B2
US 8,188,540 · App. 12/951,958 · Granted May 29, 2012

High breakdown voltage double-gate semiconductor device

Assignee: ACCO Semiconductor, Inc.
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Quick Facts
Patent No.
US 8,188,540
App. No.
12/951,958
Granted
May 29, 2012
Kind
B2
Abstract

A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.

Claims (16)

1. A device comprising:

a substrate;

a source region defined within the substrate;

a first gate including

a dielectric layer disposed on the substrate and over a channel region defined within the substrate adjoining the source region, and

an electrically conductive gate layer disposed on the dielectric layer;

a well region defined within the substrate and including

a drain region defined within the well region, and

a second gate defined within the well region between the drain region and the first gate;

an electrically conductive path between the channel region and the well region; and

control circuitry operatively connected between the first gate and the second gate and configured to couple a RF signal from the first gate to the second gate.

2. The device of claim 1 wherein the control circuitry comprises a capacitor.

3. The device of claim 1 wherein the electrically conductive path comprises a first doped region within the well adjoining a second doped region outside of the well and adjoining the channel.

4. The device of claim 1 wherein the electrically conductive path comprises a first doped region within the well adjoining the channel.

5. The device of claim 1 wherein the electrically conductive path comprises the well adjoining the channel.

6. The device of claim 1 wherein the substrate comprises P doping, the source and drain regions both comprise N doping, the well comprises N doping, and the second gate comprises P doping.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2021
From: SOMOS SEMICONDUCTOR SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 055220/0856 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2020
From: ACCO
To: SOMOS SEMICONDUCTOR
Reel/Frame 053178/0925 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2015
From: ACCO SEMICONDUCTOR INC.
To: ACCO
Reel/Frame 037370/0275 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2010
From: MASLIAH, DENIS A.; BRACALE, ALEXANDRE G.; HUIN, FRANCIS C.; BARROUL, PATRICE J.
To: ACCO SEMICONDUCTOR, INC.
Reel/Frame 025393/0971 →
Continuity (2)
Continuation 12070019 · Feb 13, 2008
Related Publication 20110068376A1 · Mar 24, 2011