Retention in NVM with top or bottom injection
Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.
1. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source,
wherein said injector further includes a hole permissive layer and an insulator layer adjacent to said hole source, and wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge storage stack.
2. The NVM cell according to claim 1 , wherein said insulator layer adjacent to said hole source is composed of an oxide.
3. The NVM cell according to claim 1 , wherein said insulator layer is at least 3 NM thick.
4. The NVM cell of claim 1 , wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
5. The NVM cell of claim 1 , wherein said charge storage layer is composed of charge trapping type material.
6. The NVM cell of claim 5 , wherein said charge trapping type material is silicon nitride.
7. The NVM cell of claim 6 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS and TONOS.
8. The NVM cell of claim 1 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
9. The NVM cell of claim 8 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
10. The NVM cell of claim 9 , wherein said injector is disposed between said stack and said gate.
11. The NVM cell of claim 9 , wherein said injector is disposed between said stack and said channel.
12. The NVM cell of claim 1 , wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
13. The NVM cell of claim 12 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
14. The NVM cell of claim 1 , wherein: said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises: a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
15. The NVM cell of claim 14 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).
16. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source adjacent to said hole source,
wherein said injector further includes a hole permissive layer and an insulator layer, and wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
17. The NVM cell according to claim 16 , wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge storage stack.
18. The NVM cell according to claim 16 , wherein said insulator layer adjacent to said hole source is composed of an oxide.
19. The NVM cell according to claim 16 , wherein said insulator layer is at least 3 NM thick.
20. The NVM cell of claim 16 , wherein said charge storage layer is composed of charge trapping type material.
21. The NVM cell of claim 20 , wherein said charge trapping type material is silicon nitride.
22. The NVM cell of claim 21 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS and TONOS.
23. The NVM cell of claim 16 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
24. The NVM cell of claim 23 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
25. The NVM cell of claim 24 , wherein said injector is disposed between said stack and said gate.
26. The NVM cell of claim 24 , wherein said injector is disposed between said stack and said channel.
27. The NVM cell of claim 16 , wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
28. The NVM cell of claim 27 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
29. The NVM cell of claim 16 , wherein: said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises: a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
30. The NVM cell of claim 29 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).
31. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source,
wherein said injector further includes a hole permissive layer and an insulator layer adjacent to said hole source, and wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
32. The NVM cell according to claim 31 , wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge storage stack.
33. The NVM cell according to claim 31 , wherein said insulator layer adjacent to said hole source is composed of an oxide.
34. The NVM cell according to claim 31 , wherein said insulator layer is at least 3 NM thick.
35. The NVM cell according to claim 31 , wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
36. The NVM cell of claim 31 , wherein said charge storage layer is composed of charge trapping type material.
37. The NVM cell of claim 36 , wherein said charge trapping type material is silicon nitride.
38. The NVM cell of claim 37 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS and TONOS.
39. The NVM cell of claim 31 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
40. The NVM cell of claim 39 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
41. The NVM cell of claim 40 , wherein said injector is disposed between said stack and said gate.
42. The NVM cell of claim 40 , wherein said injector is disposed between said stack and said channel.
43. The NVM cell of claim 31 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
44. The NVM cell of claim 31 , wherein: said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises: a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
45. The NVM cell of claim 44 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).
46. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source, wherein said injector further includes a hole permissive layer and an insulator layer adjacent to said hole source, and
wherein said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises:
a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and
a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
47. The NVM cell according to claim 46 , wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge storage stack.
48. The NVM cell according to claim 46 , wherein said insulator layer adjacent to said hole source is composed of an oxide.
49. The NVM cell according to claim 46 , wherein said insulator layer is at least 3 NM thick.
50. The NVM cell according to claim 46 , wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
51. The NVM cell of claim 46 , wherein said charge storage layer is composed of charge trapping type material.
52. The NVM cell of claim 51 , wherein said charge trapping type material is silicon nitride.
53. The NVM cell of claim 52 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS and TONOS.
54. The NVM cell of claim 46 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
55. The NVM cell of claim 54 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
56. The NVM cell of claim 55 , wherein said injector is disposed between said stack and said gate.
57. The NVM cell of claim 55 , wherein said injector is disposed between said stack and said channel.
58. The NVM cell of claim 46 , wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
59. The NVM cell of claim 58 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
60. The NVM cell of claim 46 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).