Method and system for generating timed events in a radio frame in an E-UTRA/LTE UE receiver
A mobile device coupled to a common system clock receives a signal comprising a primary synchronization sequence (PSS) and a secondary synchronization sequence (SSS) in a radio frame. Sample counts are generated for timed events based on corresponding operating bandwidths. The timed events are detected at modulo sample counts of the generated sample counts according to corresponding operating bandwidths. PSS symbol timing determined via the PSS synchronization is aligned to the generated sample counts based on corresponding operating bandwidth. The generated sample counts are bit-shifted relative to the aligned PSS symbol timing for other timed events based on corresponding operating bandwidths. The one or more timed events are determined via performing modulo counting after the bit-shifting. Timing operations are performed at the determined timed events and the determined one or more timed events are refined, accordingly.
1. A method for communication, the method comprising:
performing by one or more processors and/or circuits in a mobile device, said one or more processors and/or circuits being coupled with a system clock:
receiving a signal in a radio frame, wherein said received signal comprises a primary synchronization sequence (PSS) and a secondary synchronization sequences (SSS);
generating sample counts of said system clock for one or more timed events of said received signal in said radio frame based on corresponding operating bandwidths;
detecting said one or more timed events at modulo sample counts of said generated sample counts based on said corresponding operating bandwidths.
2. The method according to claim 1 , wherein said timed events comprise PSS symbol timing, SSS symbol timing, OFDM symbol timing, sub-frame timing, half-frame timing and/or frame timing within said radio frame.
3. The method according to claim 2 , comprising synchronizing to said received PSS to determine said PSS symbol timing.
4. The method according to claim 3 , comprising counting samples of said system clock relative to said determined PSS symbol timing for said generated sample counts.
5. The method according to claim 4 , comprising aligning said determined PSS symbol timing to said counted samples.
6. The method according to claim 5 , comprising bit-shifting said counted samples relative to said aligned PSS symbol timing for said one or more timed events based on said corresponding operating bandwidths.
7. The method according to claim 6 , comprising performing modulo counting for said one or more timed events based on said corresponding operating bandwidths after said bit-shifting.
8. The method according to claim 7 , comprising detecting said one or more timed events based on said modulo counting.
9. The method according to claim 8 , comprising performing timing operations at said detected one or more timed events.
10. The method according to claim 9 , comprising refining said detected one or more timed events based on said timing operations.
11. A system for communication, the system comprising:
one or more processors and/or circuits for use in a mobile device, wherein said one or more processors and/or circuits are coupled with a system clock, and said one or more processors and/or circuits are operable to:
receive a signal in a radio frame, wherein said received signal comprises a primary synchronization sequence (PSS) and a secondary synchronization sequences (SSS);
generate sample counts of said system clock for one or more timed events of said received signal in said radio frame based on corresponding operating bandwidths; and
detect said one or more timed events at modulo sample counts of said generated sample counts based on said corresponding operating bandwidths.
12. The system according to claim 11 , wherein said timed events comprise PSS symbol timing, SSS symbol timing, OFDM symbol timing, sub-frame timing, half-frame timing and/or frame timing within said radio frame.
13. The system according to claim 12 , wherein said one or more processors and/or circuits are operable to synchronize to said received PSS to determine said PSS symbol timing.
14. The system according to claim 13 , wherein said one or more processors and/or circuits are operable to count samples of said system clock relative to said determined PSS symbol timing for said generated sample counts.
15. The system according to claim 14 , wherein said one or more processors and/or circuits are operable to align said determined PSS symbol timing to said counted samples.
16. The system according to claim 15 , wherein said one or more processors and/or circuits are operable to bit-shift said counted samples relative to said aligned PSS symbol timing for said one or more timed events based on said corresponding operating bandwidths.
17. The system according to claim 16 , wherein said one or more processors and/or circuits are operable to perform modulo counting for said one or more timed events based on said corresponding operating bandwidths after said bit-shifting.
18. The system according to claim 17 , wherein said one or more processors and/or circuits are operable to determine said one or more timed events based on said modulo counting.
19. The system according to claim 18 , wherein said one or more processors and/or circuits are operable to perform timing operations at said determined one or more timed events.
20. The system according to claim 19 , wherein said one or more processors and/or circuits are operable to refine said determined one or more timed events based on said timing operations.