IP Library › Granted Patent US 8,189,678
Granted Patent B2
US 8,189,678 · App. 12/961,096 · Granted May 29, 2012

Video and graphics system with an MPEG video decoder for concurrent multi-row decoding

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 8,189,678
App. No.
12/961,096
Granted
May 29, 2012
Kind
B2
Abstract

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Claims (46)

1. A method of decoding video data comprising a first macroblock in a first row and a second macroblock in a second row, each macroblock is associated with a header and block layer data, the method comprising:

decoding the header of the first macroblock using a first processing element;

decoding the block layer data of the second macroblock using a second processing element; and

wherein the block layer data of the first macroblock is decoded by the second processing element after the first processing element decodes the header of the first macroblock.

2. The method of claim 1 , wherein the video data is MPEG data.

3. The method of claim 1 , wherein the video data is HDTV data.

4. The method of claim 1 , wherein a row of macroblocks is associated with a SLICE layer.

5. A method of decoding video data comprising a first macroblock in a first row and a second macroblock in a second row, each macroblock is associated with a header and block layer data, the method comprising:

decoding the header of the first macroblock using a first processing element;

decoding the block layer data of the second macroblock using a second processing element; and

wherein the second processing element decodes the block layer data of a macroblock while the first processing element decodes the header of a macroblock.

6. A method of decoding video data comprising a first macroblock in a first row and a second macroblock in a second row, each macroblock is associated with a header and block layer data, the method comprising:

decoding the header of the first macroblock using a first processing element;

decoding the block layer data of the second macroblock using a second processing element;

decoding the block layer data of the first macroblock using the second processing element; and

decoding the header of the second macroblock using the first processing element.

7. A system for decoding a video stream comprising a first macroblock in a first row and a second macroblock in a second row, each macroblock is associated with a header and video data, the system comprising:

a first processor operable to decode the header of the first macroblock;

a second processor operable to decode the video data of the second macroblock; and

wherein the first processor is operable to alternatingly decode the header of a macroblock in the first row and the header of a macroblock in the second row.

8. The system of claim 7 , wherein the video data is MPEG data.

9. The system of claim 7 , wherein the video data is HDTV data.

10. The system of claim 7 , wherein a row of one or more macroblocks is associated with a SLICE layer.

11. The system of claim 7 , wherein the first processor is operable to initiate the second processor.

12. The system of claim 7 , wherein the first processor and the second processor operate concurrently.

13. A system for decoding a video stream comprising a first macroblock in a first row and a second macroblock in a second row, each macroblock is associated with a header and video data, the system comprising:

a first processor operable to decode the header of the first macroblock;

a second processor operable to decode the video data of the second macroblock; and

wherein the second processor is operable to alternatingly decode the video data of a macroblock in the first row and decode the video data of a macroblock in the second row.

14. A system for decoding a video stream comprising a first macroblock in a first row and a second macroblock in a second row, each macroblock is associated with a header and video data, the system comprising:

a first processor operable to decode the header of the first macroblock;

a second processor operable to decode the video data of the second macroblock; and

wherein the second processor is operable to decode the video data of the first block after the header of the first block is decoded by the first processor.

15. A system for decoding a video stream comprising a first macroblock in a first row and a second macroblock in a second row, each macroblock is associated with a header and video data, the system comprising:

a first processor operable to decode the header of the first macroblock;

a second processor operable to decode the video data of the second macroblock; and

wherein the first processor is operable to decode the header of a third macroblock in a third row while the second processor decodes the video data of a last macroblock in the second row.

16. A system for decoding macroblocks in a plurality of macroblock rows, each macroblock is associated with a header and video data, the system comprising:

a first processor operable to alternate between decoding the header of a macroblock in a first row and decoding the header of a macroblock in a second row; and

a second processor operable to alternate between decoding the video data of a macroblock in the first row and decoding the video data of a macroblock in the second row;

wherein:

the second processor is operable wait for the header of a macroblock to be decoded before decoding the associated video data;

the first processor is operable to start the second processor; and

the first processor and the second processor may operate concurrently.

17. The system of claim 7 , wherein the video data is MPEG data.

18. The system of claim 7 , wherein the video data is HDTC data.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2012
From: VALMIKI, RAMANUJAN K.; BHATIA, SANDEEP
To: BROADCOM CORPORATION
Reel/Frame 028073/0614 →
Continuity (5)
Continuation 11748948 · May 15, 2007
Continuation 09641936 · Aug 18, 2000
Continuation In Part 09437208 · Nov 9, 1999
Provisional Application 60170866 · Dec 14, 1999
Related Publication 20110188580A1 · Aug 4, 2011