Method and/or apparatus for implementing reduced bandwidth high performance VC1 intensity compensation
An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal. The second circuit may be configured to generate one or more reference data pixels in response to an address signal and the output signal. The third circuit may be configured to generate the predictor signal and address signal in response to (i) the motion vectors and (ii) the reference data pixels.
1. An apparatus comprising:
a first circuit configured to generate an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal;
a second circuit configured to generate a sequence of data packets on a bus in response to (i) an address signal and (ii) said output signal, wherein each of said of said packets contains a plurality of reference data pixels; and
a third circuit configured to (i) receive said packets via said bus and (ii) generate said predictor signal and said address signal by a motion compensation of said reference data pixels received from said bus in response to said motion vectors, wherein (i) said apparatus provides said motion compensation simultaneously with a plurality of intensity compensations of said reference data pixels and (ii) said intensity compensations are performed in parallel on said reference data pixels in each of said packets.
2. The apparatus according to claim 1 , wherein said third circuit comprises a plurality of first intensity compensation circuits operating in parallel.
3. The apparatus according to claim 2 , wherein said third circuit further comprises a plurality of second intensity compensation circuits operating in parallel.
4. The apparatus according to claim 1 , wherein bitstream signal comprises a compressed bitstream.
5. The apparatus according to claim 1 , wherein said output signal comprises an uncompressed video signal.
6. The apparatus according to claim 1 , wherein said first circuit further comprises:
an entropy circuit configured to generate (i) said motion vectors and (ii) a coefficient signal, in response to said bitstream signal;
a transform circuit configured to generate an error signal in response to said coefficient signal; and
an adder circuit configured to generate said output signal in response to (i) said error signal and (ii) said predictor signal.
7. The apparatus according to claim 6 , wherein said transform circuit comprises an inverse quantization and transform circuit.
8. The apparatus according to claim 7 , wherein said third circuit comprises a motion compensation and interpolation circuit.
9. The apparatus according to claim 1 , wherein said apparatus implements said intensity compensation without using more bandwidth on said bus than needed to implement said motion compensation.
10. The apparatus according to claim 1 , wherein said apparatus is implemented in a VC1 system.
11. The apparatus according to claim 1 , wherein said second circuit comprises a plurality of intensity compensation circuits configured to generate said packets on said bus.
12. The apparatus according to claim 11 , wherein a data width of said bus matches a product of a number of said intensity compensation circuits and a bit width of said reference data pixels.
13. An apparatus comprising:
means for generating an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal;
means for generating a sequence of data packets on a bus in response to (i) an address signal and (ii) said output signal, wherein each of said of said packets contains a plurality of reference data pixels;
means for receiving said packets via said bus; and
means for generating said predictor signal and said address signal by a motion compensation of said reference data pixels received from said bus in response to said motion vectors, wherein (i) said apparatus provides said motion compensation simultaneously with a plurality of intensity compensations of said reference data pixels and (ii) said intensity compensations are performed in parallel on said reference data pixels in each of said packets.
14. A method for performing intensity compensation comprising the steps of:
(A) generating an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal;
(B) generating a sequence of data packets on a bus in response to (i) and address signal and (ii) said output signal, wherein each of said of said packets contains a plurality of reference data pixels;
(C) receiving said packets via said bus; and
(D) generating said predictor signal and said address signal by a motion compensation of said reference data pixels received from said bus in response to said motion vectors, wherein (i) said method provides said motion compensation simultaneously with a plurality of intensity compensations of said reference data pixels and (ii) said intensity compensations are performed in parallel on said reference data pixels in each of said packets.
15. The method according to claim 14 , wherein step (D) uses a plurality of first intensity compensation circuits operating in parallel.
16. The method according to claim 15 , wherein step (D) further uses a plurality of second intensity compensation circuits operating in parallel.
17. The method according to claim 14 , wherein bitstream signal comprises a compressed bitstream.
18. The method according to claim 14 , wherein said output signal comprises an uncompressed video signal.
19. The method according to claim 14 , wherein said intensity compensations are implemented in a plurality of intensity compensation circuits configured to generate said packets on said bus.
20. The method according to claim 19 , wherein a data width of said bus matches a product of a number of said intensity compensation circuits and a bit width of said reference data pixels.