Semiconductor device having vertical pillar transistors and method for manufacturing the same

1. A method for manufacturing a semiconductor device, comprising the steps of:

etching a silicon substrate to form a plurality of silicon pillars;

filling a first insulation layer into gaps between the silicon pillars, excluding gate forming gaps;

etching isotropically surfaces of lower portions of the silicon pillars in the gate forming gaps not filled with the first insulation layer;

forming gates in the lower portions of the silicon pillars which are isotropically etched;

removing the first insulation layer;

forming drain areas in portions of the silicon substrate below the gates;

forming a second insulation layer to fill the gaps between the silicon pillars having the gates selectively formed on a surface of the lower portions thereof;

forming word lines in the second insulation layer to connect gates arranged in a direction;

forming a third insulation layer to fill the gaps between the silicon pillars including the word lines;

forming source areas in portions of the silicon pillars over the gates, such that the source areas, the drain areas, and the gates constitute vertical pillar transistors; and

annealing the resultant silicon substrate formed with the source areas, such that the drain areas of the vertical pillar transistors are connected with one another, wherein the drain areas arranged perpendicular to the direction of the word lines,

wherein the gates are respectively formed only on opposite surfaces of two adjacent vertical pillar transistors, such that the gates of the two adjacent vertical pillar transistors face each other.

2. The method according to claim 1 , wherein the step of forming the silicon pillars comprises the steps of:

forming a hard mask on the silicon substrate to cover silicon pillar forming areas;

etching the silicon substrate to define first grooves;

forming first spacers on sidewalls of the first grooves and the hard mask; and

etching portions of the silicon substrate on bottoms of the first grooves using the hard mask and the first spacers as an etch mask and to define second grooves.

3. The method according to claim 2 , wherein, after the step of defining the second grooves, the method further comprises the step of:

forming second spacers on surfaces of the first spacers and the second grooves.

4. The method according to claim 1 , wherein the first insulation layer comprises an oxide layer.

5. The method according to claim 1 , wherein each of the second and third insulation layers comprises an oxide layer.

6. The method according to claim 1 , wherein the gates are buried in a single surface of the lower portion of each silicon pillar of the plurality silicon pillars.

7. The method according to claim 1 , wherein, after the step of forming the drain areas and before the step of forming the second insulation layer, the method further comprises the step of:

etching the drain areas formed in the direction perpendicular to the direction of the word lines to separate the drain areas from one another.