Standard cell having compensation capacitance

1. A standard cell, comprising:

a first well diffusion layer into which a first conductive impurity is diffused;

an insulation film provided on said first well diffusion layer;

a first wiring for applying a predetermined electric potential to said first well diffusion layer, said first wiring being connected with said first well diffusion layer via a first contact passing through said insulation film;

a first dummy pattern provided on said insulation film; and

a second wiring for applying an electric potential different from said predetermined electric potential to said first dummy pattern, wherein

said standard cell includes a first capacity element which is made up of said first dummy pattern, said insulation film and said first well diffusion layer.

2. The standard cell according to claim 1 , comprising a first transistor element including a source electrode and a drain electrode, which are provided in said first well diffusion layer and which are made up of a diffusion layer that has a second conductive impurity whose conductivity is an opposite type to said first conductive impurity, and including a gate electrode provided in the same layer with said first dummy pattern.

3. The standard cell according to claim 2 , further comprising:

a second well diffusion layer into which said second conductive impurity is diffused;

a third wiring for applying the same electric potential as said electric potential of said second wiring to said second well diffusion layer, said third wiring being connected with said second well diffusion layer via a second contact passing through said insulation film;

a second transistor element including a source electrode and a drain electrode, which are provided in said second well diffusion layer and which are made up of a diffusion layer whose conductivity is the same type to said first conductive impurity and including a gate electrode provided in the same layer with said first dummy pattern; and

a second dummy pattern provided on said insulation film, wherein

said standard cell includes a second capacity element which is made up of said second dummy pattern, said insulation film and said second well diffusion layer.

4. The standard cell according to claim 3 , wherein each of said first and second dummy patterns includes:

a third dummy pattern provided in the same layer with said gate electrode and in parallel with said gate electrode of a corresponding transistor element; and

a fourth dummy pattern for keeping a pattern density per unit area within a predetermined range, said fourth dummy pattern being provided in the same layer with said gate electrode.

5. The standard cell according to claim 4 , wherein

an outer shape of said standard cell is a rectangle;

an active pattern, in which said insulation film is formed on a part of an upper face of said first well diffusion layer, is provided in an inner edge of each of two long-sides and one short-side of said rectangle along each side; and

said third dummy pattern is provided between said first transistor element and said active pattern provided along said long-sides.

6. The standard cell according to claim 5 , wherein

said fourth dummy pattern is provided between said first transistor element and said active pattern provided along said short-side.

7. The standard cell according to claim 5 , wherein

said fourth dummy pattern is provided above said active pattern which is provided along said short-side, via said insulation film.

8. A semiconductor device, comprising a plurality of the standard cells according to claim 3 , wherein

a plurality of said standard cells are disposed such that said first or second capacity elements of adjacent standard cells are overlapped.

9. The standard cell according to claim 2 , wherein

an outer shape of said standard cell is a rectangle;

an active pattern, in which said insulation film is formed on a part of an upper face of said first well diffusion layer, is provided in an inner edge of each of two long-sides and one short-side of said rectangle along each side; and

a site of said active pattern, at which said first contact is connected to said first well diffusion layer, and said first dummy pattern are alternately provided along each side of said long-sides and said short-side.

10. A semiconductor device, comprising:

a first well diffusion layer made of a first conductive type;

first and second active patterns, which are made of said first conductive type, for respectively supplying a first electric potential to said first well diffusion layer, said first and second active patterns being provided in said first well diffusion layer; and

a first capacity provided in said first well diffusion layer, one terminal of said first capacity being supplied with said first electric potential, wherein

said first capacity is configured to be interposed between said first and second active patterns.

11. The semiconductor device according to claim 10 , further comprising:

a second well diffusion layer, which is made of a second conductive type, provided adjacent to said first well diffusion layer; and

a third active pattern, which is made of said second conductive type, for supplying a second electric potential to said second well diffusion layer, said third active pattern being provided in said second well diffusion layer, wherein

the other terminal of said first capacity is electrically connected with said third active pattern.

12. The semiconductor device according to claim 11 , further comprising:

a fourth active pattern, which is made of said second conductive type, for supplying said second electric potential to said second well diffusion layer, said fourth active pattern being provided in said second well diffusion layer; and

a second capacity provided in said second well diffusion layer, one terminal of said second capacity being electrically connected with either said first or said second active patterns or with both said first and said second active patterns, and the other terminal being supplied with said second electric potential, wherein

said second capacity is configured to be interposed between said third and fourth active patterns.

13. The semiconductor device according to claim 11 , further comprising:

a first transistor including fifth and sixth active patterns provided in said first well diffusion layer, said fifth and sixth active patterns being made of said second conductive type; and

a second transistor including seventh and eighth active patterns provided in said second well diffusion layer, said seventh and eighth active patterns being made of said first conductive type.

14. The semiconductor device according to claim 10 , further comprising:

a first transistor including fifth and sixth active patterns provided in said first well diffusion layer, said fifth and sixth active patterns being made of said second conductive type.

15. A semiconductor device comprising:

a first well region;

first and second active patterns formed in the first well region with sandwiching a part of the first well region therebetween, each of the first and second active patterns being equal in conductivity type to that of the first well region and supplied with a first potential to supply the first potential to the first well region; and

a wiring formed over the part of the first well region with an intervention of an insulating film therebetween, the wiring being supplied with a second potential different from the first potential,

the part of the first well, the wiring, and the insulating film constituting a capacitor.

16. The semiconductor device according to claim 15 , further comprising a first transistor including third and fourth active patterns formed in the first well region, each of the third and fourth active patterns being different in conductivity type from the first well region.

17. The semiconductor device according to claim 16 , wherein the third active pattern is supplied with the first potential and electrically independent of the fourth active pattern.

18. The semiconductor device according to claim 15 , further comprising:

a second well region different in conductivity type from the first well region; and

a fifth active pattern formed in the second well region, the fifth active pattern being equal in conductivity type to that of the second well region and supplied with the second potential to supply the second potential to the second well region.

19. The semiconductor device according to claim 18 , further comprising:

a sixth active pattern formed in the second well region apart from the fifth active pattern such that the fifth and sixth active pattern sandwich a part of the second well region therebetween; and

an additional wiring formed over the part of the second well region with an intervention of an additional insulating film therebetween, the wiring being supplied with the first potential,

the part of the second well, the additional wiring and the additional insulating film constituting an additional capacitor.

20. A semiconductor device comprising:

a first well region;

a plurality of active patterns formed in the first well region apart from each other to define at least one part of the first well region sandwiched by an adjacent two of the active patterns, each of the active patterns being equal in conductivity type to the first well region and supplied with a first potential; and

at least one wiring pattern formed over the at least one part of the first well region with an intervention of an insulating film, and the wiring pattern being supplied with a second potential different from the first potential.

21. The semiconductor device according to claim 20 , wherein three or more active patterns are arranged in line to form two or more gaps between adjacent two of active patterns, and each of two or more wiring patterns being formed over the gap between associated adjacent two of the active patterns.

22. The semiconductor device according to claim 20 , further comprising:

a second well region different in conductivity type from that of the first well region;

a plurality of additional active patterns formed in the first well region apart from each other to form at least one additional gap between adjacent two of the additional active patterns, each of the additional active patterns being equal in conductivity type to the second well region and supplied with the second potential; and

at least one additional wiring pattern formed over the additional gap with an intervention of an additional insulating film, and the additional wiring pattern being supplied with the first potential.