Granted Patent B2

US 8,203,182 · App. 12/529,640 · Granted Jun 19, 2012

Assignees: NXP B.V.; ST Microelectronics (Crolles 2) SAS

Abstract

Claims (37)

1. A Fin field effect transistor, FinFET, comprising

a fin-shaped layer-section of a single-crystalline active semiconductor layer extending on an insulating substrate layer along a longitudinal fin direction between a source layer-section and a drain layer-section of the single-crystalline active semiconductor layer,

gate insulation layers arranged on two opposite side faces of the fin-shaped layer-section, and

two separate gate-electrode layers, which do not form sections of the single-crystalline active semiconductor layer, each of the gate-electrode layers facing one of the opposite side faces of the fin-shaped layer-section, and each gate-electrode layer being connected with a respective separate gate contact, wherein each of the gate-electrode layers, as seen in a cross-sectional view of a plane that is perpendicular to the longitudinal fin-direction, is arranged on the substrate layer between the respective side face of the fin-shaped layer section and a respective contact-post layer section of the single-crystalline semiconductor layer;

wherein the gate contacts are arranged abutting a top face of the respective contact-post layer section of the single-crystalline active semiconductor layer and a side face of the respective gate-electrode layer.

2. The FinFET of claim 1 , wherein the gate contacts have the shape of an L turned upside down, the vertical bar of the L extending perpendicularly to the substrate layer from the contact-post layer section to increasing distances from the substrate layer, the horizontal bar of the L being arranged on the respective gate-electrode layer.

3. The FinFET of claim 1 , wherein the fin-shaped layer-section and the contact-post layer sections of the single-crystalline semiconductor layer on the substrate layer have an equal thickness (h).

4. The FinFET of claim 3 , wherein the source and drain layer sections and the fin-shaped layer-section of the single-crystalline semiconductor layer on the substrate layer have an equal thickness (h).

5. The FinFET of claim 1 , comprising a metal silicide layer between the contact-post layer sections of the active semiconductor layer and the gate contacts.

6. The FinFET of claim 1 , wherein a lateral distance (d) between the fin-shaped layer section and a respective contact-post layer section of the single-crystalline semiconductor layer is smaller than 2 times the thickness of the gate-electrode layer.

7. A FinFET arrangement containing a plurality of neighboring FinFETs according to claim 1 , wherein two neighboring FinFETs share one gate electrode layer, one contact-post layer section and one gate contact.

8. The FinFet arrangement of claim 6 , wherein the shared gate contact has a T-shape, and two wings of the horizontal T-bar of the gate contact are arranged on gate-electrode layers of the neighboring FinFETs, which share the gate contact.

9. A method for fabricating a Fin field effect transistor, FinFET, comprising the steps:

providing a substrate with a single-crystalline active semiconductor layer extending on an insulating substrate layer;

patterning the active semiconductor layer to form source and drain layer sections, a fin-shaped layer section extending along a longitudinal fin direction between the source layer-section and the drain layer-section, and two allocated contact-post layer sections at a distance (d) to two opposite side faces of the fin-shaped layer-section,

fabricating gate insulation layers on the two opposite side faces of the fin-shaped layer-section,

fabricating two gate-electrode layers on the substrate layer, each of the two gate-electrode layers facing one of the opposite side faces of the fin-shaped layer-section and filling the distance (d) between the fin-shaped layer section and the respective contact-post layer section, and,

fabricating separate gate contacts, each connecting with one respective gate electrode layer;

wherein before patterning the active semiconductor layer a step of depositing a hard mask is performed, which hard-mask is stable against a first etching agent that attacks the gate-electrode layers;

wherein the depositing the hard mask comprises depositing a first hard-mask layer on the active semiconductor layer and a second hard-mask layer on the first hard-mask layer, wherein the first and second hard-mask layers are mutually stable against etching agents that attack the respective other hard-mask layer; and

comprising the steps:

selectively removing the second hard mask layer from the source and drain layer sections after patterning the gate-electrode material layer;

selectively removing the first hard mask layer from the source and drain layer sections;

forming a metal silicide on a surface of the source, drain and gate-electrode layer sections of the active semiconductor layer, and on a surface of portions of the fin-shaped layer-section outside the channel regions;

removing the second and first hard-mask sections from the contact-post layer sections of the active semiconductor layer;

conformally depositing a dielectric layer;

fabricating openings in the dielectric layer that reach to the surface of the contact-post layer sections;

fabricating contacts in the openings, wherein the contacts abut the surface of the respective contact-post layer section and a side face of the respective gate-electrode layers.

10. The method of claim 9 , wherein fabricating the gate-electrode layers comprises

conformally depositing a contiguous gate-electrode-material layer on the patterned active semiconductor layer;

patterning the gate-electrode-material layer to cover only a strip extending in one lateral direction from the first contact-post layer section to the second contact-post layer section, and in a second lateral direction, which corresponds to the longitudinal direction of the fin-shaped layer section, over desired channel regions of the fin-shaped layer section between the source and drain layer sections,

etching the gate-electrode material layer anisotropically until the reaching the second hard-mask layer, thus separating the gate-electrode material layer into the two gate-electrode layers.

11. The method of claim 9 , comprising the steps

removing the hard mask from the contact posts and from the source and drain layer sections after patterning the gate-electrode material layer;

fabricating a dielectric layer that covers the fin-shaped layer section;

selectively depositing semiconductor material on the contact posts and on the source and drain layer sections;

siliciding the semiconductor material.

Assignments (10)

Priority Claims (1)

Continuity (1)