Image display device and testing method of the same
View Patent ↗It is the primary object of the present invention to provide a simple and accurate testing circuit and a testing method while occupying as small space as possible in an image display device. The testing circuit including a NAND circuit connected in series is mounted on the image display device. A broken wiring on a data signal line and a defect in a data latch circuit can be detected by observing an output waveform from the testing circuit. Accordingly, a broken wiring or the like on the data signal line and a scanning line and a defect in the latch circuit can be tested simply and accurately without an expensive testing apparatus and a great deal of time while occupying as small space as possible.
1. A display device comprising:
a pixel portion including at least two data signal lines over a substrate;
a driver circuit operationally connected to the pixel portion so as to supply signals to the data signal lines;
a circuit operationally connected to the pixel portion, the circuit including:
a plurality of two input NAND circuits over the substrate, connected in series wherein a first input of one of the plurality of two input NAND circuits is directly connected to an output of another one of the plurality of two input NAND circuits,
wherein each of a second input of the plurality of two input NAND circuits is connected to one of the data signal lines, and
wherein the data signal lines are connected to a plurality of pixels.
2. The display device according to claim 1 ,
wherein a first input of the first of the plurality of two input NAND circuits connected in series is connected to a power source.
3. The display device according to claim 1 ,
wherein an output of the last of the plurality of two input NAND circuits connected in series is connected to a testing terminal.
4. The display device according to claim 1 , wherein the circuit is a test circuit.
5. A testing method of a display device including:
a pixel portion including at least two data signal lines over a substrate;
a driver circuit operationally connected to the pixel portion so as to supply signals to the data signal lines;
a circuit over the substrate, operationally connected to the pixel portion, the circuit including:
a plurality of two input NAND circuits connected in series, wherein a first input of one of the plurality of two input NAND circuits is directly connected to an output of another one of the plurality of two input NAND circuits, wherein each of a second input of the plurality of two input NAND circuits is connected to one of the data signal lines, and wherein the data signal lines are connected to a plurality of pixels,
the testing method comprising:
adding a voltage to a first input of the first of the plurality of two input NAND circuits connected in series;
inputting a testing pulse to the data signal lines; and
comparing a wave form of the testing pulse and a wave form of an output of the last of the plurality of two input NAND circuits connected in series.
6. The testing method according to claim 5 ,
wherein the testing pulse is a High signal in all the data signal lines and is switched sequentially into a Low signal.
7. The testing method according to claim 5 ,
wherein the testing pulse is a pulse output to the data signal lines in accordance with an input of a video signal.
8. A display device comprising:
a pixel portion including at least two data signal lines over a substrate;
a driver circuit over the substrate, operationally connected to the pixel portion so as to supply signals to the data signal lines;
a circuit operationally connected to the pixel portion, the circuit including:
a plurality of two input NAND circuits connected in series wherein a first input of one of the plurality of two input NAND circuits is connected to an output of another one of the plurality of two input NAND circuits,
wherein each of a second input of the plurality of two input NAND circuits is directly connected to one of the data signal lines, and
wherein the data signal lines are connected to a plurality of pixels.
9. The display device according to claim 8 ,
wherein a first input of the first of the plurality of two input NAND circuits connected in series is connected to a power source.
10. The display device according to claim 8 ,
wherein an output of the last of the plurality of two input NAND circuits connected in series is connected to a testing terminal.
11. The display device according to claim 8 ,
wherein the first input of one of the plurality of two input NAND circuits is directly connected to the output of another one of the plurality of two input NAND circuits.
12. The display device according to claim 8 , wherein the circuit is a test circuit.
13. A display device comprising:
a pixel portion including at least two bus lines over a substrate;
a driver circuit operationally connected to the pixel portion so as to supply signals to the bus lines;
a circuit over the substrate, operationally connected to the pixel portion, the circuit including:
a plurality of two input NAND circuits connected in series wherein a first input of one of the plurality of two input NAND circuits is directly connected to an output of another one of the plurality of two input NAND circuits,
wherein each of a second input of the plurality of two input NAND circuits is connected to one of the bus lines,
wherein the bus lines are connected to a plurality of pixels.
14. The display device according to claim 13 ,
wherein a first input of the first of the plurality of two input NAND circuits connected in series is connected to a power source.
15. The display device according to claim 13 ,
wherein an output of the last of the plurality of two input NAND circuits connected in series is connected to a testing terminal.
16. The display device according to claim 13 , wherein the circuit is a test circuit.
17. A display device comprising:
a pixel portion including at least two bus lines over a substrate;
a driver circuit operationally connected to the pixel portion so as to supply signals to the bus lines;
a circuit over the substrate, operationally connected to the pixel portion, the circuit including:
a plurality of two input NAND circuits connected in series wherein a first input of one of the plurality of two input NAND circuits is connected to an output of another one of the plurality of two input NAND circuits,
wherein each of a second input of the plurality of two input NAND circuits is directly connected to one of the bus lines,
wherein the bus lines are connected to a plurality of pixels.
18. The display device according to claim 17 ,
wherein a first input of the first of the plurality of two input NAND circuits connected in series is connected to a power source.
19. The display device according to claim 17 ,
wherein an output of the last of the plurality of two input NAND circuits connected in series is connected to a testing terminal.
20. The display device according to claim 17 ,
wherein the first input of one of the plurality of two input NAND circuits is directly connected to the output of another one of the plurality of two input NAND circuits.
21. The display device according to claim 17 , wherein the circuit is a test circuit.