ADPLL circuit, semiconductor device, and portable information device
The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.
1. An ADPLL circuit comprising:
a digitally controlled oscillator;
a digital phase comparator for detecting a phase error between a frequency division signal obtained by dividing frequency of an output of the digitally controlled oscillator and a reference signal; and
an ABS circuit for performing automatic frequency selection,
wherein the ABS circuit has therein a digital frequency comparator for detecting a shift direction of a phase error between the frequency division signal and the reference signal from an output of the digital frequency comparator, and
wherein the digital frequency comparator includes a first D-flip flop for storing a shift amount of the phase error between the frequency division signal and the reference signal in beginning of start of the ABS operation of the digital phase comparator.
2. The ADPLL circuit according to claim 1 , wherein the digital frequency comparator comprises a subtractor for subtracting the shift amount of the phase error stored in the first D-flip flop from an output of the digital phase comparator which is input.
3. The ADPLL circuit according to claim 2 , wherein the digital frequency comparator detects a shift direction of the phase error by using sign of a value obtained by subtracting the shift amount of the phase error stored in the first D-flip flop from the output of the digital phase comparator.
4. The ADPLL circuit according to claim 3 ,
wherein the ABS circuit further comprises a binary search device,
wherein a band signal configured by two or more signal lines is output from the binary search device, and
wherein a value of any one of the signal lines of the band signal is determined by supplying a shift direction of the phase error from the digital frequency comparator to the binary search device.
5. The ADPLL circuit according to claim 4 , further comprising a digital low-pass filter,
wherein the band signal and an output of the digital phase comparator via the digital low-pass filter are input to the digitally controlled oscillator.
6. The ADPLL circuit according to claim 4 , further comprising an analog phase comparator and a selector circuit,
wherein the selector circuit selects which one of an output of the digital phase comparator and an output of the analog phase comparator is input to the binary search device.
7. A semiconductor device comprising the ADPLL circuit according to claim 1 .
8. A portable information device comprising the semiconductor device according to claim 7 .
9. A semiconductor device comprising the ADPLL circuit according to claim 2 .
10. A semiconductor device comprising the ADPLL circuit according to claim 3 .
11. A semiconductor device comprising the ADPLL circuit according to claim 4 .
12. A semiconductor device comprising the ADPLL circuit according to claim 5 .
13. A semiconductor device comprising the ADPLL circuit according to claim 6 .