IP Library Granted Patent US 8,212,356
Granted Patent B2
US 8,212,356 · App. 12/873,570 · Granted Jul 3, 2012

Semiconductor device having multi-layered wiring layer and fabrication process thereof

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 8,212,356
App. No.
12/873,570
Granted
Jul 3, 2012
Kind
B2
Abstract

A semiconductor device having a multi-layered wiring layer includes a semiconductor substrate, an electrode that is provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate, the insulating film having an aperture at least partly overlapping the electrode, a resin bump that is provided on the insulating film, and the wiring layer that is electrically connected to the electrode and that includes a first conductive layer, an intermediate layer, and a second conductive layer. The first conductive layer is formed on the electrode and on the resin bump, the intermediate layer is formed on the first conductive layer, and the second conductive layer formed on the intermediate layer.

Claims (29)

1. A semiconductor device comprising:

a semiconductor substrate that has a first surface and a second surface opposite to the first surface;

an electrode that is provided on the first surface of the semiconductor substrate;

an insulating film that is provided on the first surface of the semiconductor substrate, the insulating film having an aperture at least partly overlapping the electrode;

a resin bump that is provided on the insulating film; and

a wiring layer that is electrically connected to the electrode, a part of the wiring layer being provided on the resin bump, the wiring layer that includes a first conductive layer, an intermediate layer, and a second conductive layer, wherein

the first conductive layer is formed on the electrode and on the resin bump, the intermediate layer is formed on the first conductive layer, and the second conductive layer is formed on the intermediate layer.

2. The semiconductor device according to claim 1 , further includes a base layer that is formed between the first conductive layer and the resin bump.

3. The semiconductor device according to claim 2 , wherein the base layer is formed between the first conductive layer and the following three areas of the electrode, the insulating film, and the resin bump.

4. The semiconductor device according to claim 1 , wherein the first conductive layer includes any one of titanium, nickel, chromium, and tungsten, and wherein the second conductive layer includes any one of gold, platinum, and copper.

5. An electronic component electrically connected to the semiconductor device of claim 1 .

6. A semiconductor device fabrication process comprising:

preparing a structure that includes: a semiconductor substrate that has a first surface and a second surface opposite to the first surface; an electrode provided on the first surface of the semiconductor substrate; and an insulating film provided on the first surface of the semiconductor substrate, the insulating film including an aperture at least partly overlapping the electrode;

forming a resin bump on the insulating film; and

forming a wiring layer electrically connected to the electrode, the wiring layer that includes a first conductive layer, an intermediate layer, and a second conductive layer, wherein

the forming the wiring layer further includes:

forming the first conductive layer on the electrode and on the resin bump;

forming the intermediate layer on the first conductive layer by oxidizing or nitriding an upper surface of the first conductive layer; and

forming the second conductive layer on the intermediate layer.

7. The semiconductor device fabrication process according to claim 6 , wherein

the wiring layer further includes a base layer formed between the first conductive layer and the resin bump, the forming the wiring layer further include:

forming an additional conductive layer, which has the same material as the first conductive layer, on the resin bump before the first conductive layer is formed; and

heating the additional conductive layer in an atmosphere of oxygen or nitride so as to form the base layer.

8. The semiconductor device fabrication process according to claim 6 , wherein

the wiring layer further includes a base layer formed between the first conductive layer and the resin bump, and

the forming the wiring layer further include heating the first conducting layer in an atmosphere of oxygen or nitride so as to change a bottom surface of the first conductive layer into a base layer formed between the first conductive layer and the resin bump, and change the upper surface of the first conductive layer into the intermediate layer.

9. An electronic component fabrication process comprising:

preparing a semiconductor device fabricated by the semiconductor device fabrication process of claim 6 ; and

electrically connecting the semiconductor device to a wiring substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 1, 2024
From: SEIKO EPSON CORPORATION
To: CRYSTAL LEAP ZRT
Reel/Frame 066162/0434 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2010
From: YAMASAKI, YASUO
To: SEIKO EPSON CORPORATION
Reel/Frame 024923/0441 →
Priority Claims (1)
JP 2009-262166 · Nov 17, 2009 · national
Continuity (1)
Related Publication 20110115076A1 · May 19, 2011