Method and systems for power consumption management of a pattern-recognition processor
Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. In some embodiments, the pattern-recognition processor includes a first block of feature cells coupled to a decoder via a first plurality of local input conductors, a first block-disabling circuit, and a plurality of global input conductors. The pattern-recognition processor further includes a second block of feature cells coupled to the decoder via a second plurality of local input conductors, a second block-disabling circuit, and the plurality of global input conductors.
1. A device, comprising:
a pattern-recognition processor comprising:
a decoder;
a first block of feature cells coupled to the decoder via a first plurality of local input conductors, a first block-disabling circuit, and a plurality of global input conductors; and
a second block of feature cells coupled to the decoder via a second plurality of local input conductors, a second block-disabling circuit, and the plurality of global input conductors;
wherein the first block-disabling circuit is configured to disable the first block of features cells if the first block of features cells is inactive; and
wherein the second block-disabling circuit is configured to disable the second block of features cells if the second block of features cells is inactive.
2. The device of claim 1 , wherein each of the first plurality of local input conductors is coupled to one of a plurality of memory cells in each feature cell in the first block of feature cells.
3. The device of claim 1 , wherein the decoder is coupled to an input data stream and the pattern-recognition processor is configured to search the data stream according to a plurality of search criteria encoded by the first block of feature cells and the second block of feature cells.
4. The device of claim 1 , wherein the first block-disabling circuit comprises a plurality of AND gates each having an output terminal coupled to one of the local input conductors among the first plurality of local input conductors.
5. The device of claim 4 , wherein the plurality of AND gates each have an input terminal coupled to one of the global input conductors among the plurality of global input conductors.
6. The device of claim 4 , wherein the plurality of AND gates each have an input terminal coupled to an output terminal of an OR gate.
7. The device of claim 6 , wherein the OR gate has a plurality of input terminals each coupled to a detection cell in one of the feature cells in the first plurality of feature cells.
8. The device of claim 6 , wherein the OR gate has a plurality of input terminals each coupled to a memory cell configured to output a value indicative of whether one or more feature cells in the first plurality of feature cells is active.
9. The device of claim 6 , wherein the OR gate comprises a plurality of input terminals each coupled to a memory cell in a detection cell in one of the feature cells in the first plurality of feature cells.
10. The device of claim 4 , wherein the plurality of AND gates each comprise an input terminal coupled to a memory cell.
11. The device of claim 10 , comprising an activation-routing matrix coupled to the memory cell, wherein the activation-routing matrix is configured to store a value in the memory cell that is indicative of whether any feature cells in the first plurality of feature cells is active.
12. The device of claim 1 , wherein the first block of feature cells comprises more than 255 feature cells and the second block of feature cells comprises more than 255 feature cells.
13. A method, comprising:
receiving a signal from a global input conductor;
determining via block disabling circuitry whether any feature cells in a block of feature cells is active; and
if at least one feature cell in the block of feature cells is active, transmitting the signal from the global input conductor through the block disabling circuitry to a local input conductor coupled to the block of feature cells; and
if no feature cell in the block of feature cells is active, disabling the block of features cells via the block-disabling circuitry.
14. The method of claim 13 , wherein receiving a signal from a global input conductor comprises receiving a signal from a global input conductor coupled to a plurality of blocks of feature cells.
15. The method of claim 13 , wherein receiving a signal from a global input conductor comprises receiving a signal from a decoder.
16. The method of claim 13 , wherein determining whether any feature cells in a block of feature cells is active comprises outputting a signal from an OR gate coupled to each of the feature cells in the block of feature cells.
17. The method of claim 13 , wherein determining whether any feature cells in the block of feature cells is active comprises outputting a value stored by a memory cell, wherein the value is indicative of whether any of the feature cells in the block of feature cells is active.
18. The method of claim 13 , wherein transmitting the signal from the global input conductor to the local input conductor comprises transmitting the signal from the output terminal of an AND gate.
19. The method of claim 13 , wherein transmitting the signal from the global input conductor to the local input conductor comprises transmitting the signal from the global input conductor to a plurality of local input conductors each associated with different blocks of feature cells including at least one active feature cell.
20. The method of claim 13 , comprising searching a data stream according to search criteria.
21. The method of claim 20 , comprising receiving the search criteria from a remote server.
22. A system, comprising:
a processing unit (PU); and
a pattern-recognition processor coupled to the PU, wherein the pattern-recognition processor comprises
one or more blocks, each comprising one or more feature cells; and
one or more block-disabling circuits connected to the one or more blocks, wherein each of the one or more block-disabling circuits is configured to disable a respective one of the one or more blocks if the respective one of the one or more blocks is inactive.
23. The system of claim 22 , wherein the pattern-recognition processor comprises a plurality of blocks of feature cells, and wherein each block of feature cells among the plurality of blocks of feature cells is associated with one of the block-disabling circuits among the plurality of block-disabling circuits.
24. The system of claim 22 , wherein each block-disabling circuit among the plurality of block-disabling circuits is configured to selectively prevent signals from a data stream being searched by the pattern-recognition processor from reaching a block of feature cells that does not include any active feature cells.
25. The system of claim 22 , wherein the pattern-recognition processor comprises a row decoder coupled to each of the block-disabling circuits among the plurality of block-disabling circuits.
26. The system of claim 25 , wherein the pattern-recognition processor comprises a plurality of global input conductors that couple the row decoder to each of the block-disabling circuits among the plurality of block-disabling circuits.
27. The system of claim 26 , wherein the pattern-recognition processor comprises a plurality of local input conductors selectively coupled to each of the plurality of global input conductors by the plurality of block-disabling circuits.
28. The system of claim 26 , wherein the pattern-recognition processor comprises:
a plurality of blocks of feature cells, each block coupled to one of the block disabling circuits;
an activation-routing matrix coupled to each of the blocks of feature cells; and
an aggregation module coupled to each of the blocks of feature cells.
29. The system of claim 22 , wherein the PU and the pattern recognition module are part of a network switch, a router, a personal computer, or a server.
30. A method, comprising:
receiving a data stream;
searching the data stream via a pattern recognition processor according to search criteria, wherein each of the search criteria comprises a plurality of search terms, and wherein the plurality of search terms are grouped into a first block of search terms and a second block of search terms;
determining at block-disabling circuitry whether any search terms in the first block of search terms is active; and
if no search terms in the first block of search terms are active, disabling the first block of search terms.
31. The method of claim 30 , wherein receiving the data stream comprises receiving a packet of data over a network.
32. The method of claim 30 , wherein the search terms are encoded in memory in feature cells.
33. The method of claim 30 , comprising:
determining whether any search terms in the second block of search terms is active; and
if no search terms in the second block of search terms are active, disabling the second block of search terms.
34. The method of claim 30 , wherein disabling the first block of search terms comprises preventing a signal from being transmitted between a global input conductor and a local input conductor associated with the first block of search terms.