IC with first and second external register present leads
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15 , test data output leads 13 , control leads 17 and an external register present, ERP lead 37 . A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
1. An integrated circuit comprising:
A. a semiconductor substrate;
B. functional IP core circuits formed on the substrate, the IP core circuits forming a periphery on the substrate and having core functional input leads and core functional output leads that extend beyond that periphery; and
C. test circuits formed on the substrate within the periphery of the functional IP core circuits, the test circuits including:
i. a test data input lead extending beyond the periphery of the functional IP core circuits;
ii. a test data output lead extending beyond the periphery of the functional IP core circuits;
iii. a test clock lead extending beyond the periphery of the functional IP core circuits;
iv. a test mode select lead extending beyond the periphery of the functional IP core circuits;
v. a test access port coupled to the test data input lead, the test data output lead, the test clock lead, and the test mode select lead;
vi. test data registers coupled to the test data input lead, and the test data output lead;
vii. an instruction register coupled to the test data input lead and the test data output lead;
viii. a first external register present lead separate from the test data input lead and the test data output lead, connected to the instruction register and extending beyond the periphery of the functional IP core circuits; and
ix. a second external register present lead separate from the test data input lead and the test data output lead, connected to the instruction register and extending beyond the periphery of the functional IP core circuits.
2. The integrated circuit of claim 1 in which the instruction register includes a capture-shift-update register section and the external register present lead is connected to the capture-shift-update register section.
3. The integrated circuit of claim 1 in which the instruction register includes a decode section and the first and second external register present leads are connected to the decode section.
4. The integrated circuit of claim 1 in which the instruction register includes a capture-shift-update register section and a decode section and the first and second external register present leads are connected to the capture-shift-update register section and the decode section.
5. The integrated circuit of claim 1 in which the first and second external register present leads are only input leads that carry only input signals.