IP Library Granted Patent US 8,218,650
Granted Patent B2
US 8,218,650 · App. 13/039,606 · Granted Jul 10, 2012

Context adaptive binary arithmetic decoding for high definition video

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,218,650
App. No.
13/039,606
Granted
Jul 10, 2012
Kind
B2
Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.

Claims (11)

1. An apparatus comprising:

a first circuit configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal; and

a second circuit configured to, in parallel (i) generate said binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information, wherein said second circuit is configured to (i) parse H.264 bin grammar of said one or more bins, (ii) determine a syntax element from said H.264 bin grammar and a bit index position within said determined syntax element and (iii) pre-decode said syntax elements needed to calculate a first context information and a second context information, wherein (A) said second circuit is configured to calculate said second context information by evaluating whether said value of said bin currently decoded in said first circuit is a second predetermined value, (B) said second circuit is configured to select (i) said first context information if said bin currently decoded in said first circuit is said first predetermined value and (ii) said second context information if said bin currently decoded in said first circuit is said second predetermined value and (C) said second circuit comprises a bin state machine configured to present data of a current macroblock.

2. The apparatus according to claim 1 , wherein said second circuit comprises an arithmetic decoder configured to arithmetically decode said context information.

3. The apparatus according to claim 2 , wherein said second circuit comprises a first context determination circuit configured to calculate said first context information by evaluating whether a value of said bin currently being decoded in said first circuit is a first predetermined value.

4. The apparatus according to claim 3 , wherein said second circuit comprises a second context determination circuit.

5. The apparatus according to claim 4 , wherein said second circuit comprises a multiplexer.

6. The apparatus according to claim 2 , wherein said second circuit comprises one or more registers configured to generate data of a left neighboring macroblock in response to data of a current neighboring macroblock.

7. The apparatus according to claim 6 , wherein said second circuit comprises a synchronous dynamic access memory configured to generate data for an above neighboring macroblock in response to said data of a current neighboring macroblock.

8. The apparatus according to claim 7 , wherein said first circuit comprises a decoder configured to (i) decode said one or more bins on said binary signal and (ii) generate said video signal and said macroblock data.

9. The apparatus according to claim 1 , wherein said bitstream signal comprises a high definition bitstream.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Apr 24, 2012
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 028095/0941 →
MERGER Recorded Apr 21, 2011
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 026163/0232 →
Continuity (2)
Continuation 11331404 · Jan 12, 2006
Related Publication 20110150075A1 · Jun 23, 2011