Nonsequential hardware design synthesis verification
View Patent ↗Methods and apparatuses for verifying a concurrent logical design and a corresponding non-sequential algorithmic description are provided. In some implementations, verification of a non-sequential algorithmic description for a device design is facilitated by monitoring a simulation of the non-sequential algorithmic description and synchronizing the timing of selected events with timing from an already completed simulation of a corresponding logical design. With various implementations, the hierarchical blocks in the logical design are monitored during the prior simulation to record selected event information. Subsequently, the recorded event information may be used to synchronize the simulation of the non-sequential algorithmic description.
1. A computer-implemented method for enabling a verification of a non-sequential hardware design synthesis, the method comprising:
identifying a non-sequential algorithmic description for a hardware design;
identifying a register transfer level description corresponding to the hardware design;
identifying a simulation run implemented on the register transfer level description;
logging inputs applied to the register transfer level description during the simulation run;
logging selected events occurring during the simulation run;
logging outputs received from the register transfer level description during the simulation run;
implementing a verification run on the non-sequential algorithmic description, wherein the logged inputs are used as inputs to the verification run, and the logged selected events are synchronized with corresponding events in the verification run; and
saving outputs from the verification run to a memory storage location.
2. The computer-implemented method recited in claim 1 , the method act for logging selected events occurring during the simulation run comprising:
identifying a channel within the simulation run;
monitoring the channel during the simulation run; and
recording events occurring on the channel during the simulation run onto a non-transitory memory storage location.
3. The computer-implemented method recited in claim 2 , wherein the events are: inputs to the channel;
outputs from the channel;
requests to read data from the channel; and requests to write data to the channel.
4. The computer-implemented method recited in claim 3 , the method act for implementing a verification run on the non-sequential algorithmic description comprising:
causing the non-sequential algorithmic description to be simulated, wherein the logged inputs are used as inputs to a simulation;
identifying a channel within the simulation that corresponds to the channel within the simulation run;
monitoring the channel during the simulation; and
synchronizing recorded event data with the channel during the simulation run.
5. The computer-implemented method recited in claim 4 , the method act of synchronizing recorded event data comprises causing the data within the channel to correspond to the recorded event data.
6. The computer-implemented method recited in claim 5 , further comprising:
comparing the logged outputs to the saved outputs, wherein a result is generated;
saving the result to a non-transitory memory storage location; and
providing the result to a user.
7. The computer-implemented method recited in claim 2 , wherein the events are inputs to the channel.
8. The computer-implemented method recited in claim 2 , wherein the events are outputs of the channel.
9. The computer-implemented method recited in claim 2 , wherein the events are requests to read data from the channel.
10. The computer-implemented method recited in claim 2 , wherein the events are requests to write data to the channel.
11. One or more non-transitory computer-readable media having computer executable instructions stored thereon, the one or more non-transitory computer-readable media comprising:
a plurality of computer executable instructions for causing a computer to perform a method non-transitorily stored thereon, the method including:
identifying a non-sequential algorithmic description for a hardware design;
identifying a register transfer level description corresponding to the hardware design;
identifying a simulation run implemented on the register transfer level description;
logging inputs applied to the register transfer level description during the simulation run;
logging selected events occurring during the simulation run;
logging outputs received from the register transfer level description during the simulation run;
implementing a verification run on the non-sequential algorithmic description, wherein the logged inputs are used as inputs to the verification run, and the logged events are synchronized with corresponding events in the verification run; and
saving outputs from the verification run to a memory storage location.
12. The one or more non-transitory computer-readable media recited in claim 11 , the method act for logging selected events occurring during the simulation run comprising:
identifying a channel within the simulation run;
monitoring the channel during the simulation run; and
recording events occurring on the channel during the simulation run onto a non-transitory memory storage location.
13. The one or more non-transitory computer-readable media recited in claim 12 , wherein the events are:
inputs to the channel;
outputs from the channel;
requests to read data from the channel; and
requests to write data to the channel.
14. The one or more non-transitory computer-readable media recited in claim 13 , the method act for implementing a verification run on the non-sequential algorithmic description comprising:
causing the non-sequential algorithmic description to be simulated, wherein the logged inputs are used as inputs to a simulation;
identifying a channel within the simulation that corresponds to the channel within the simulation run;
monitoring the channel during the simulation; and
synchronizing recorded event data with the channel during the simulation run.
15. The one or more non-transitory computer-readable media recited in claim 14 , the method act of synchronizing recorded event data comprises causing the data within the channel to correspond to the recorded event data.
16. The one or more non-transitory computer-readable media recited in claim 15 , the method further comprising:
comparing the logged outputs to the saved outputs, wherein a result is generated;
saving the result to a non-transitory memory storage location; and
providing the result to a user.
17. A system for verifying a non-sequentially synthesized circuit design comprising:
a first simulation module configured to implement a simulation of an algorithmic description corresponding to an electronic design;
a second simulation module configured to implement a simulation of the electronic design;
a simulation monitoring module configured to monitor the simulation of the electronic design and capture event data related to the simulation of the electronic design;
a simulation synchronization module configured to synchronize the captured event data with the simulation of the algorithmic description; and
a simulation result comparison module configured to compare a result of the simulation of the algorithmic description and a result of the simulation of the electronic design.