IP Library Granted Patent US 8,222,528
Granted Patent B2
US 8,222,528 · App. 12/045,140 · Granted Jul 17, 2012

Circuit board structure for electrical testing and fabrication method thereof

Assignee: Unimicron Technology Corp.
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Quick Facts
Patent No.
US 8,222,528
App. No.
12/045,140
Granted
Jul 17, 2012
Kind
B2
Abstract

The invention provides a circuit board structure for electrical testing and a fabrication method thereof. The circuit board structure includes: a core board having a plurality of first circuits, an electroplating conductive wires, and distributing wires for electrical connection thereof; a dielectric layer formed on the core board, the first circuits, the distributing wires and the electroplating conductive wires, wherein the dielectric layer is formed with at least one opening for exposing the distributing wires; a plurality of second circuit formed on the dielectric layer and electrically connected to the first circuits; a solder mask layer formed on the dielectric layer and the second circuits; and at least one first opening formed in the solder mask layer, above the distributing wires, and deep into the dielectric layer to create a broken circuit between the distributing wires and the electroplating conductive wires, thus enabling electrical testing of the circuit board structure, and reducing noise interference.

Claims (13)

1. A circuit board structure for electrical testing, comprising:

a core board having a plurality of first circuits, distributing wires and electroplating conductive wires formed thereon, wherein two ends of the distributing wires respectively connect the first circuits and the electroplating conductive wires;

a dielectric layer formed on surfaces of the core board, the first circuits, the distributing wires and the electroplating conductive wires, wherein at least an opening is formed in the dielectric layer to expose the distributing wires;

a plurality of second circuits formed on a surface of the dielectric layer and electrically connected to the first circuits;

a solder mask layer formed on surfaces of the dielectric layer and the second circuits; and

at least a first opening formed in the solder mask layer, on top of the distributing wires, and deep into the dielectric layer and the distributing wires, so as to create a broken circuit between the first circuits and the electroplating conductive wires, wherein the first opening is disposed above the opening formed in the dielectric layer, and the first opening has an aperture larger than that of the opening, the opening being formed in stepwise, thereby enabling electrical testing of the circuit board structure.

2. The circuit board structure of claim 1 further comprising a plurality of conductive structure electrically connecting the first circuits and the second circuits.

3. The circuit board structure of claim 2 , wherein the conductive structure is one of a plated through hole and a conductive blind via.

4. The circuit board structure of claim 1 , wherein the second circuits have a plurality of electrically connecting pads.

5. The circuit board structure of claim 4 further comprising a metal protection layer formed on the surfaces of the electrically connecting pads.

6. The circuit board structure of claim 5 , wherein the metal protection layer is made of one selected from the group consisting of Pb, Sn, Ag, Cu, Au, Bi, Sb, Zn, Ni, Zr, Mg, In, Te, Ga, and an alloy thereof.

7. The circuit board structure of claim 5 , wherein the solder mask layer further comprises a second opening for exposing the metal protection layer on the surfaces of the electrically connecting pads.

8. The circuit board structure of claim 1 , wherein the broken circuit is created in the distributing wires by a chemical means.

Assignments (2)
MERGER Recorded Jun 13, 2012
From: PHOENIX PRECISION TECHONOLOGY CORPORATION
To: UNIMICRON TECHNOLOGY CORP.
Reel/Frame 028366/0871 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2008
From: CHOU, PAO-HUNG
To: PHOENIX PRECISION TECHNOLOGY CORPORATION
Reel/Frame 020622/0824 →
Continuity (1)
Related Publication 20080185177A1 · Aug 7, 2008