Double and triple gate MOSFET devices and methods for making same
A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.
1. A triple gate metal-oxide semiconductor field-effect transistor (MOSFET), comprising:
a silicon fin including a left side surface and a right side surface;
a capping layer formed on top of the fin,
where the capping layer causes the fin to be strained, and
where a left side surface of the capping layer is substantially aligned with the left side surface of the fin and a right side surface of the capping layer is substantially aligned with a right side surface of the fin;
a first gate structure formed on top of the capping layer, a left side surface of the first gate structure being substantially aligned with the left side surface of the capping layer and the left side surface of the silicon fin, and a right side surface of the first gate structure being substantially aligned with the right side surface of the capping layer and the right side surface of the silicon fin;
a second gate structure formed adjacent the fin; and
a third gate structure formed adjacent the fin and opposite the second gate structure, the first gate structure, the second gate structure, and the third gate structure being separated from each other.
2. The triple gate MOSFET of claim 1 , where the first gate structure, the second gate structure, and the third gate structure are to independently control the fin.
3. The triple gate MOSFET of claim 1 , where the second gate structure and the third gate structure include a same gate material.
4. A double gate metal-oxide semiconductor field-effect transistor (MOSFET), comprising:
a silicon fin including a left side surface and a right side surface;
a capping layer formed on top of the fin,
where the capping layer causes the fin to be strained, and
where a left side surface of the capping layer is substantially aligned with the left side surface of the fin and a right side surface of the capping layer is substantially aligned with a right side surface of the fin;
a first gate formed on top of the capping layer, a left side surface of the first gate being substantially aligned with the left side surface of the capping layer and the left side surface of the silicon fin, and a right side surface of the first gate being substantially aligned with the right side surface of the capping layer and the right side surface of the silicon fin; and
a second gate structure that surrounds the fin and the first gate.
5. The double gate MOSFET of claim 4 , where the first gate and the second gate are to independently control the fin.
6. The double gate MOSFET of claim 4 further comprising:
a cover layer and a dielectric layer formed between the first gate and the second gate.
7. The triple gate MOSFET of claim 1 , where a width of the silicon fin ranges from approximately 50 Å to 500 Å.
8. The triple gate MOSFET of claim 1 , where a thickness of the silicon fin ranges from approximately 200 Å to 1000 Å.
9. The triple gate MOSFET of claim 1 , where a top surface of the second gate structure and a top surface of the third gate structure are below a top surface of the first gate structure.
10. The double gate MOSFET of claim 4 , where a width of the silicon fin ranges from approximately 50 Å to 500 Å.
11. The double gate MOSFET of claim 4 , where a thickness of the silicon fin ranges from approximately 200 Å to 1000 Å.
12. The triple gate MOSFET of claim 1 , where the capping layer comprises a stressed film layer.
13. The triple gate MOSFET of claim 1 , where the capping layer comprises a nitride-based material.
14. The double gate MOSFET of claim 4 , where the capping layer comprises a stressed film layer.
15. The double gate MOSFET of claim 4 , where the capping layer comprises a nitride-based material.