Structures for preventing cross-talk between through-silicon vias and integrated circuits
View Patent ↗A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.
1. A semiconductor chip comprising:
a through-substrate via (TSV) extending through a semiconductor substrate, the TSV being a signal-carrying TSV;
a device region; and
a cross-talk prevention ring comprising a first portion in a metallization layer over the semiconductor substrate, the first portion encircling the device region, wherein the TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring, the cross-talk prevention ring comprising a conductive material.
2. The semiconductor chip of claim 1 further comprising a seal ring adjacent to edges of the semiconductor chip, wherein the seal ring encircles the cross-talk prevention ring, and wherein the TSV is between the seal ring and the cross-talk prevention ring.
3. The semiconductor chip of claim 2 further comprising a sacrificial ring between the seal ring and the edges of the semiconductor chip.
4. The semiconductor chip of claim 2 further comprising a plurality of TSVs between the seal ring and the cross-talk prevention ring.
5. The semiconductor chip of claim 1 , wherein the cross-talk prevention ring encircles an additional TSV.
6. The semiconductor chip of claim 1 further comprising a seal ring adjacent to edges of the semiconductor chip, wherein the cross-talk prevention ring comprises a seal ring extension and a portion of the seal ring.
7. The semiconductor chip of claim 6 , wherein the cross-talk prevention ring comprises a corner portion of the seal ring.
8. The semiconductor chip of claim 6 , wherein the cross-talk prevention ring comprises an edge and two corner portions of the seal ring.
9. The semiconductor chip of claim 1 , wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion is conductive and is electrically connected to the first portion.
10. The semiconductor chip of claim 1 , wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion comprises a dielectric material.
11. The semiconductor chip of claim 1 , wherein the cross-talk prevention ring is grounded.
12. The semiconductor chip of claim 1 further comprising a plurality of TSVs, each encircled by an additional grounded cross-talk prevention ring.
13. The semiconductor chip of claim 1 , further comprising
a seal ring comprising four sides, each being adjacent to an edge of the semiconductor chip, wherein the cross-talk prevention ring is encircled by the seal ring, wherein the cross-talk prevention ring comprises four sides, each being adjacent to one of the sides of the seal ring, wherein the cross-talk prevention ring is grounded, and wherein the TSV is located in a region between the seal ring and the cross-talk prevention ring.
14. The semiconductor chip of claim 13 , wherein the region between the seal ring and the cross-talk prevention ring is substantially free from active devices.
15. The semiconductor chip of claim 13 further comprising a plurality of TSVs distributed in the region between the seal ring and the cross-talk prevention ring.
16. The semiconductor chip of claim 13 , wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion is conductive and is electrically connected to the first portion.
17. The semiconductor chip of claim 13 , wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion comprises a dielectric material.
18. The semiconductor chip of claim 1 , further comprising
a seal ring comprising four sides, each being adjacent to an edge of the semiconductor chip; and
a seal ring extension comprising a first end and a second end, each physically connected to a portion of the seal ring, wherein the seal ring extension and the seal ring form the cross-talk prevention ring encircling a first region of the semiconductor die, and wherein the first region is substantially free from active devices, the TSV being located in the first region, a second region outside the cross-talk prevention ring comprising active devices.
19. The semiconductor chip of claim 18 , wherein the first region further comprises additional TSVs.