Interface circuit and video apparatus
An interface circuit includes: a first transmitting section transmitting a first signal as an in-phase signal to an external device through a transmission path; and a second transmitting section transmitting a clock signal, which is synchronized with the first signal to be transmitted by the first transmitting section, as a differential signal to the external device through the transmission path.
1. An interface circuit comprising:
a first transmitting section transmitting a first signal as an in-phase signal to an external device through a transmission path; and
a second transmitting section transmitting a clock signal, which is synchronized with the first signal to be transmitted by the first transmitting section, as a differential signal to the external device through the transmission path,
in which the clock signal is reproducible by the external device without use of a phase lock loop (PLL),
the transmission path is a twisted pair formed by a reserve line and a hot plug detect line of a high-definition multimedia interface cable.
2. The interface circuit according to claim 1 , further comprising:
a transmitting/receiving section transmitting a second signal as a second differential signal to the external device through the transmission path and processing a third differential signal, which is received from the external device through the transmission path, so as to receive the second signal,
wherein the second transmitting section transmits the clock signal when the transmitting/receiving section does not transmit or receive the second signal.
3. The interface circuit according to claim 1 , further comprising:
a first receiving section processing a second in-phase signal, which is received from the external device through the transmission path, so as to receive the first signal; and
a second receiving section processing a second differential signal, which is received from the external device through the transmission path, so as to receive the clock signal, which is synchronized with the first signal to be received by the first receiving section.
4. An interface circuit comprising:
a first receiving section processing an in-phase signal, which is received from an external device through a transmission path, so as to receive a first signal; and
a second receiving section processing a differential signal, which is received from the external device through the transmission path, so as to receive a clock signal, which is synchronized with the first signal to be received by the first receiving section,
in which the clock signal is obtained by the second receiving section without use of a phase lock loop (PLL)),
the transmission path is a twisted pair formed by a reserve line and a hot plug detect line of a high-definition multimedia interface cable.
5. The interface circuit according to claim 4 , further comprising:
a transmitting/receiving section transmitting a second signal as a second differential signal to the external device through the transmission path and processing a third differential signal, which is received from the external device through the transmission path, so as to receive the second signal,
wherein the second receiving section receives the clock signal when the transmitting/receiving section does not transmit or receive the second signal.