Bond pad for wafer and package for CMOS imager
View Patent ↗An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.
1. An electronic package including a semiconductor chip having a plurality of electrically connected layers arranged on a substrate and at least one bond pad positioned on an upper surface of said semiconductor chip, said electronic package comprising structure extending between said at least one bond pad and said substrate for protecting electrical connections and components contained therein from an ingress of moisture and contaminants, wherein said protective structure includes an edge seal and a crack stop each forming a ring-shaped arrangement extending in a mutually spaced relationship about the periphery of said at least one bond pad.
2. An electronic package as claimed in claim 1 , wherein a through-via for packaging leads extends through said substrate layer and active layers of said semiconductor chip to said bond pads.
3. An electronic package as claimed in claim 1 , wherein said edge seal extends partially about the edge portion of the respective bond pads in an active layer, which is located on said substrate layer.
4. An electronic package as claimed in claim 1 , wherein said bond pad array is located on said substrate layer, and at least one probe pad comprises a top layer of said electronic package, said edge seal having an upper portion forming an opening with a lower edge seal portion so as to facilitate connection of said bond pads to the interior of said semiconductor chip in the absence of being electrically connected to said edge seal.
5. An electronic package as claimed in claim 1 , wherein a through-via extends through the substrate layer and bond pads to tungsten contacts or higher metal layers in the electronic package; the edge seal extending from the top layer to a Si 3 N 4 layer located on said substrate layer so as to, in conjunction with the crack stop, protect the electrical component and devices in the package from the ingress of moisture and contaminants.
6. An electronic package as claimed in claim 1 , wherein said edge seal and crack stop inhibit the ingress of moisture and contaminants from the rear edge and sides of said electronic package.
7. An electronic package as claimed in claim 6 , wherein said crack stop prevents the propagation of cracks and fissures into said electronic package resulting from dicing cuts separating said semiconductor chip from a wafer.
8. An electronic package as claimed in claim 1 , wherein said edge seal and crack stop extend between a capping layer between said bond pad array and said substrate layer.
9. An electronic package as claimed in claim 8 , wherein said capping layer comprises Si 3 N 4 and is located on an uppermost electrically-conductive metal layer.
10. An electronic package as claimed in claim 8 , wherein said substrate layer comprises Si and contains active devices which are protected by said edge seal and crack stop arrangements.